Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami

Research output: Contribution to journalArticle

192 Citations (Scopus)

Abstract

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.

Original languageEnglish
Pages (from-to)463-471
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume33
Issue number3
DOIs
Publication statusPublished - 1998 Mar
Externally publishedYes

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Keywords

  • Clocks
  • CMOS integrated circuits
  • Design automation
  • Flip-flops
  • Integrated circuit layout
  • Low power
  • Timing
  • Voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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