Automated selective multi-threshold design for ultra-low standby applications

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa

Research output: Contribution to conferencePaperpeer-review

60 Citations (Scopus)

Abstract

This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

Original languageEnglish
Pages202-206
Number of pages5
DOIs
Publication statusPublished - 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: 2002 Aug 122002 Aug 14

Conference

ConferenceProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period02/8/1202/8/14

Keywords

  • Automated design
  • Multi-threshold
  • Standby leakage current

ASJC Scopus subject areas

  • Engineering(all)

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