Automated selective multi-threshold design for ultra-low standby applications

Kimiyoshi Usami; Naoyuki Kawabe; Masayuki Koizumi; Katsuhiro Seta; Toshiyuki Furusawa

doi:10.1109/lpe.2002.146737

Automated selective multi-threshold design for ultra-low standby applications

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa

Research output: Contribution to conference › Paper › peer-review

64 Citations (Scopus)

Abstract

This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

Original language	English
Pages	202-206
Number of pages	5
DOIs	https://doi.org/10.1109/lpe.2002.146737
Publication status	Published - 2002
Externally published	Yes
Event	Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: 2002 Aug 12 → 2002 Aug 14

Conference

Conference	Proceedings of the 2002 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey, CA
Period	02/8/12 → 02/8/14

Keywords

Automated design
Multi-threshold
Standby leakage current

ASJC Scopus subject areas

Engineering(all)

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10.1109/lpe.2002.146737

Cite this

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title = "Automated selective multi-threshold design for ultra-low standby applications",

abstract = "This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.",

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author = "Kimiyoshi Usami and Naoyuki Kawabe and Masayuki Koizumi and Katsuhiro Seta and Toshiyuki Furusawa",

year = "2002",

doi = "10.1109/lpe.2002.146737",

language = "English",

pages = "202--206",

note = "Proceedings of the 2002 International Symposium on Low Power Electronics and Design ; Conference date: 12-08-2002 Through 14-08-2002",

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T1 - Automated selective multi-threshold design for ultra-low standby applications

AU - Usami, Kimiyoshi

AU - Kawabe, Naoyuki

AU - Koizumi, Masayuki

AU - Seta, Katsuhiro

AU - Furusawa, Toshiyuki

PY - 2002

Y1 - 2002

N2 - This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

AB - This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

KW - Automated design

KW - Multi-threshold

KW - Standby leakage current

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M3 - Paper

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T2 - Proceedings of the 2002 International Symposium on Low Power Electronics and Design

Y2 - 12 August 2002 through 14 August 2002

ER -

Automated selective multi-threshold design for ultra-low standby applications

Abstract

Conference

Keywords

ASJC Scopus subject areas

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