Automated selective multi-threshold design for ultra-low standby applications

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)

Abstract

This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
Pages202-206
Number of pages5
Publication statusPublished - 2002
Externally publishedYes
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA
Duration: 2002 Aug 122002 Aug 14

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CityMonterey, CA
Period02/8/1202/8/14

Fingerprint

Transistors
Sleep

Keywords

  • Automated design
  • Multi-threshold
  • Standby leakage current

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Usami, K., Kawabe, N., Koizumi, M., Seta, K., & Furusawa, T. (2002). Automated selective multi-threshold design for ultra-low standby applications. In Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers (pp. 202-206)

Automated selective multi-threshold design for ultra-low standby applications. / Usami, Kimiyoshi; Kawabe, Naoyuki; Koizumi, Masayuki; Seta, Katsuhiro; Furusawa, Toshiyuki.

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. 2002. p. 202-206.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Kawabe, N, Koizumi, M, Seta, K & Furusawa, T 2002, Automated selective multi-threshold design for ultra-low standby applications. in Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. pp. 202-206, Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, 02/8/12.
Usami K, Kawabe N, Koizumi M, Seta K, Furusawa T. Automated selective multi-threshold design for ultra-low standby applications. In Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. 2002. p. 202-206
Usami, Kimiyoshi ; Kawabe, Naoyuki ; Koizumi, Masayuki ; Seta, Katsuhiro ; Furusawa, Toshiyuki. / Automated selective multi-threshold design for ultra-low standby applications. Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. 2002. pp. 202-206
@inproceedings{cda0d50f79cf40dfbb7d5e275443c927,
title = "Automated selective multi-threshold design for ultra-low standby applications",
abstract = "This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14{\%} over the single high-Vth design without increasing standby leakage at 10{\%} area overhead.",
keywords = "Automated design, Multi-threshold, Standby leakage current",
author = "Kimiyoshi Usami and Naoyuki Kawabe and Masayuki Koizumi and Katsuhiro Seta and Toshiyuki Furusawa",
year = "2002",
language = "English",
pages = "202--206",
booktitle = "Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers",

}

TY - GEN

T1 - Automated selective multi-threshold design for ultra-low standby applications

AU - Usami, Kimiyoshi

AU - Kawabe, Naoyuki

AU - Koizumi, Masayuki

AU - Seta, Katsuhiro

AU - Furusawa, Toshiyuki

PY - 2002

Y1 - 2002

N2 - This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

AB - This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.

KW - Automated design

KW - Multi-threshold

KW - Standby leakage current

UR - http://www.scopus.com/inward/record.url?scp=0036957192&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036957192&partnerID=8YFLogxK

M3 - Conference contribution

SP - 202

EP - 206

BT - Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

ER -