Buffer-trap and surface-state effects on gate lag in AlGaN/GaN HEMTs

Kazushige Horio, Atsushi Nakajima

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.

Original languageEnglish
Pages (from-to)1931-1933
Number of pages3
JournalPhysica Status Solidi (C) Current Topics in Solid State Physics
Volume7
Issue number7-8
DOIs
Publication statusPublished - 2010

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high electron mobility transistors
time lag
buffers
traps
electrons
electric potential
simulation

Keywords

  • AlGaN/GaN
  • Design
  • HEMTs
  • Simulation
  • Surface states
  • Trap levels

ASJC Scopus subject areas

  • Condensed Matter Physics

Cite this

Buffer-trap and surface-state effects on gate lag in AlGaN/GaN HEMTs. / Horio, Kazushige; Nakajima, Atsushi.

In: Physica Status Solidi (C) Current Topics in Solid State Physics, Vol. 7, No. 7-8, 2010, p. 1931-1933.

Research output: Contribution to journalArticle

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