Buffer-trapping effects on drain lag and power compression in GaN FET

K. Horio, K. Yonemoto

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Buffer-trapping effects in a GaN MESFET are studied by two-dimensional transient simulation. A three-level compensation model is adopted for a semi-insulating buffer layer where a shallow donor, a deep donor and a deep acceptor are considered. It is shown that when the drain voltage VD is raised, the drain current overshoots the steady-state value, and when VD is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET.

Original languageEnglish
Pages (from-to)2635-2638
Number of pages4
JournalPhysica Status Solidi C: Conferences
Volume2
Issue number7
DOIs
Publication statusPublished - 2005 Nov 7

ASJC Scopus subject areas

  • Condensed Matter Physics

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