Buffer-trapping effects on drain lag and power compression in GaN FET

Kazushige Horio, K. Yonemoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Buffer-trapping effects in a GaN MESFET are studied by two-dimensional transient simulation. A three-level compensation model is adopted for a semi-insulating buffer layer where a shallow donor, a deep donor and a deep acceptor are considered. It is shown that when the drain voltage VD is raised, the drain current overshoots the steady-state value, and when V D is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET.

Original languageEnglish
Title of host publicationPhysica Status Solidi C: Conferences
Pages2635-2638
Number of pages4
Volume2
Edition7
DOIs
Publication statusPublished - 2005

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ASJC Scopus subject areas

  • Condensed Matter Physics

Cite this

Horio, K., & Yonemoto, K. (2005). Buffer-trapping effects on drain lag and power compression in GaN FET. In Physica Status Solidi C: Conferences (7 ed., Vol. 2, pp. 2635-2638) https://doi.org/10.1002/pssc.200461311