Cache controller design on ultra low leakage embedded processors

Zhao Lei, Hui Xu, Naomi Seki, Saito Yoshiki, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano

Research output: Contribution to journalArticle

Abstract

A leakage-efficient cache controller design targeted on ultra low power embedded processors is proposed. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the fine-grained run-time power gating technique, such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control policies are proposed to assure the leakage reduction effect; and to eliminate the impact of wake-up process, a latency cancellation mechanism is also proposed. Evaluation results show, in 90nm CMOS technology, 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation.

Original languageEnglish
Pages (from-to)171-182
Number of pages12
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5455 LNCS
DOIs
Publication statusPublished - 2009

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Controllers
Degradation
Networks (circuits)

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Cache controller design on ultra low leakage embedded processors. / Lei, Zhao; Xu, Hui; Seki, Naomi; Yoshiki, Saito; Hasegawa, Yohei; Usami, Kimiyoshi; Amano, Hideharu.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 5455 LNCS, 2009, p. 171-182.

Research output: Contribution to journalArticle

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