Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS generation

Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.

Original languageEnglish
Pages (from-to)848-855
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE90-C
Issue number4
DOIs
Publication statusPublished - 2007 Apr

Keywords

  • Application
  • CMOS
  • Copper
  • Design
  • Interconnect
  • Low-k

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Oda, N., Imura, H., Kawahara, N., Tagami, M., Kunishima, H., Sone, S., Ohnishi, S., Yamada, K., Kakuhara, Y., Sekine, M., Hayashi, Y., & Ueno, K. (2007). Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS generation. IEICE Transactions on Electronics, E90-C(4), 848-855. https://doi.org/10.1093/ietele/e90-c.4.848