Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, Kazuyoshi Ueno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel interconnect design concept named "ASIS (Application-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
Pages1022-1025
Number of pages4
Volume2005
Publication statusPublished - 2005
Externally publishedYes
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD
Duration: 2005 Dec 52005 Dec 7

Other

OtherIEEE International Electron Devices Meeting, 2005 IEDM
CityWashington, DC, MD
Period05/12/505/12/7

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Electric wiring
Wire
Metals

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Oda, N., Imura, H., Kawahara, N., Tagami, M., Kunishima, H., Sone, S., ... Ueno, K. (2005). Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. In Technical Digest - International Electron Devices Meeting, IEDM (Vol. 2005, pp. 1022-1025). [1609538]

Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. / Oda, N.; Imura, H.; Kawahara, N.; Tagami, M.; Kunishima, H.; Sone, S.; Ohnishi, S.; Yamada, K.; Kakuhara, Y.; Sekine, M.; Hayashi, Y.; Ueno, Kazuyoshi.

Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2005 2005. p. 1022-1025 1609538.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Oda, N, Imura, H, Kawahara, N, Tagami, M, Kunishima, H, Sone, S, Ohnishi, S, Yamada, K, Kakuhara, Y, Sekine, M, Hayashi, Y & Ueno, K 2005, Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. in Technical Digest - International Electron Devices Meeting, IEDM. vol. 2005, 1609538, pp. 1022-1025, IEEE International Electron Devices Meeting, 2005 IEDM, Washington, DC, MD, 05/12/5.
Oda N, Imura H, Kawahara N, Tagami M, Kunishima H, Sone S et al. Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. In Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2005. 2005. p. 1022-1025. 1609538
Oda, N. ; Imura, H. ; Kawahara, N. ; Tagami, M. ; Kunishima, H. ; Sone, S. ; Ohnishi, S. ; Yamada, K. ; Kakuhara, Y. ; Sekine, M. ; Hayashi, Y. ; Ueno, Kazuyoshi. / Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2005 2005. pp. 1022-1025
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AU - Sone, S.

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