Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, K. Ueno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel interconnect design concept named "ASIS (Application-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages1022-1025
Number of pages4
Publication statusPublished - 2005 Dec 1
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
Duration: 2005 Dec 52005 Dec 7

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2005
ISSN (Print)0163-1918

Conference

ConferenceIEEE International Electron Devices Meeting, 2005 IEDM
CountryUnited States
CityWashington, DC, MD
Period05/12/505/12/7

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Oda, N., Imura, H., Kawahara, N., Tagami, M., Kunishima, H., Sone, S., Ohnishi, S., Yamada, K., Kakuhara, Y., Sekine, M., Hayashi, Y., & Ueno, K. (2005). Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest (pp. 1022-1025). [1609538] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005).