Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, K. Ueno

Research output: Contribution to journalArticle

5 Citations (Scopus)
Original languageEnglish
Pages (from-to)848-855
JournalIEICE Transaction on Electronics
VolumeE90-C
Publication statusPublished - 2007 Apr 15

Cite this

Oda, N., Imura, H., Kawahara, N., Tagami, M., Kunishima, H., Sone, S., ... Ueno, K. (2007). Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation. IEICE Transaction on Electronics, E90-C, 848-855.

Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation. / Oda, N.; Imura, H.; Kawahara, N.; Tagami, M.; Kunishima, H.; Sone, S.; Ohnishi, S.; Yamada, K.; Kakuhara, Y.; Sekine, M.; Hayashi, Y.; Ueno, K.

In: IEICE Transaction on Electronics, Vol. E90-C, 15.04.2007, p. 848-855.

Research output: Contribution to journalArticle

Oda, N, Imura, H, Kawahara, N, Tagami, M, Kunishima, H, Sone, S, Ohnishi, S, Yamada, K, Kakuhara, Y, Sekine, M, Hayashi, Y & Ueno, K 2007, 'Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation', IEICE Transaction on Electronics, vol. E90-C, pp. 848-855.
Oda N, Imura H, Kawahara N, Tagami M, Kunishima H, Sone S et al. Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation. IEICE Transaction on Electronics. 2007 Apr 15;E90-C:848-855.
Oda, N. ; Imura, H. ; Kawahara, N. ; Tagami, M. ; Kunishima, H. ; Sone, S. ; Ohnishi, S. ; Yamada, K. ; Kakuhara, Y. ; Sekine, M. ; Hayashi, Y. ; Ueno, K. / Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation. In: IEICE Transaction on Electronics. 2007 ; Vol. E90-C. pp. 848-855.
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AU - Sone, S.

AU - Ohnishi, S.

AU - Yamada, K.

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