Chip-package co-design for suppressing parallel resonance and power supply noise

Tatsuya Mido, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Yoshinori Kobayashi, Hideyuki Fujii, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

Original languageEnglish
Title of host publication2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Pages347-350
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 - Tempe, AZ, United States
Duration: 2012 Oct 212012 Oct 24

Publication series

Name2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012

Conference

Conference2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
CountryUnited States
CityTempe, AZ
Period12/10/2112/10/24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Mido, T., Kobayashi, R., Kubo, G., Otsuka, H., Kobayashi, Y., Fujii, H., & Sudo, T. (2012). Chip-package co-design for suppressing parallel resonance and power supply noise. In 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 (pp. 347-350). [6457913] (2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012). https://doi.org/10.1109/EPEPS.2012.6457913