Chip-package co-design for suppressing parallel resonance and power supply noise

Tatsuya Mido, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Yoshinori Kobayashi, Hideyuki Fujii, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

Original languageEnglish
Title of host publication2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Pages347-350
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 - Tempe, AZ
Duration: 2012 Oct 212012 Oct 24

Other

Other2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
CityTempe, AZ
Period12/10/2112/10/24

Fingerprint

Electric power distribution
Damping
Networks (circuits)
Logic circuits
Signal interference
Electric power systems
Electromagnetic waves
Degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mido, T., Kobayashi, R., Kubo, G., Otsuka, H., Kobayashi, Y., Fujii, H., & Sudo, T. (2012). Chip-package co-design for suppressing parallel resonance and power supply noise. In 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 (pp. 347-350). [6457913] https://doi.org/10.1109/EPEPS.2012.6457913

Chip-package co-design for suppressing parallel resonance and power supply noise. / Mido, Tatsuya; Kobayashi, Ryota; Kubo, Genki; Otsuka, Hiroki; Kobayashi, Yoshinori; Fujii, Hideyuki; Sudo, Toshio.

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012. 2012. p. 347-350 6457913.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mido, T, Kobayashi, R, Kubo, G, Otsuka, H, Kobayashi, Y, Fujii, H & Sudo, T 2012, Chip-package co-design for suppressing parallel resonance and power supply noise. in 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012., 6457913, pp. 347-350, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012, Tempe, AZ, 12/10/21. https://doi.org/10.1109/EPEPS.2012.6457913
Mido T, Kobayashi R, Kubo G, Otsuka H, Kobayashi Y, Fujii H et al. Chip-package co-design for suppressing parallel resonance and power supply noise. In 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012. 2012. p. 347-350. 6457913 https://doi.org/10.1109/EPEPS.2012.6457913
Mido, Tatsuya ; Kobayashi, Ryota ; Kubo, Genki ; Otsuka, Hiroki ; Kobayashi, Yoshinori ; Fujii, Hideyuki ; Sudo, Toshio. / Chip-package co-design for suppressing parallel resonance and power supply noise. 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012. 2012. pp. 347-350
@inproceedings{2afe04e3ae9648e0a76070d91dff0553,
title = "Chip-package co-design for suppressing parallel resonance and power supply noise",
abstract = "Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.",
author = "Tatsuya Mido and Ryota Kobayashi and Genki Kubo and Hiroki Otsuka and Yoshinori Kobayashi and Hideyuki Fujii and Toshio Sudo",
year = "2012",
doi = "10.1109/EPEPS.2012.6457913",
language = "English",
isbn = "9781467325394",
pages = "347--350",
booktitle = "2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012",

}

TY - GEN

T1 - Chip-package co-design for suppressing parallel resonance and power supply noise

AU - Mido, Tatsuya

AU - Kobayashi, Ryota

AU - Kubo, Genki

AU - Otsuka, Hiroki

AU - Kobayashi, Yoshinori

AU - Fujii, Hideyuki

AU - Sudo, Toshio

PY - 2012

Y1 - 2012

N2 - Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

AB - Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

UR - http://www.scopus.com/inward/record.url?scp=84874489787&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874489787&partnerID=8YFLogxK

U2 - 10.1109/EPEPS.2012.6457913

DO - 10.1109/EPEPS.2012.6457913

M3 - Conference contribution

SN - 9781467325394

SP - 347

EP - 350

BT - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012

ER -