Clock-gating method for low-power LSI design

Takeshi Kitahara; Fumihiro Minami; Toshiaki Ueda; Kimiyoshi Usami; Seiichi Nishio; Masami Murakata; Takashi Mitsuhashi

Clock-gating method for low-power LSI design

Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

Original language	English
Pages	307-312
Number of pages	6
Publication status	Published - 1998 Dec 1
Externally published	Yes
Event	Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn Duration: 1998 Feb 10 → 1998 Feb 13

Other

Other	Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
City	Yokohama, Jpn
Period	98/2/10 → 98/2/13

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

Clock-gating method for low-power LSI design. / Kitahara, Takeshi; Minami, Fumihiro; Ueda, Toshiaki; Usami, Kimiyoshi; Nishio, Seiichi; Murakata, Masami; Mitsuhashi, Takashi.

1998. 307-312 Paper presented at Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn.

Research output: Contribution to conference › Paper › peer-review

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abstract = "This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.",

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AU - Murakata, Masami

AU - Mitsuhashi, Takashi

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Clock-gating method for low-power LSI design

Abstract

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ASJC Scopus subject areas

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