Abstract
This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 307-312 |
| Number of pages | 6 |
| Publication status | Published - 1998 |
| Externally published | Yes |
| Event | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn Duration: 1998 Feb 10 → 1998 Feb 13 |
Other
| Other | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) |
|---|---|
| City | Yokohama, Jpn |
| Period | 98/2/10 → 98/2/13 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Clock-gating method for low-power LSI design. / Kitahara, Takeshi; Minami, Fumihiro; Ueda, Toshiaki; Usami, Kimiyoshi; Nishio, Seiichi; Murakata, Masami; Mitsuhashi, Takashi.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. p. 307-312.Research output: Chapter in Book/Report/Conference proceeding › Chapter
}
TY - CHAP
T1 - Clock-gating method for low-power LSI design
AU - Kitahara, Takeshi
AU - Minami, Fumihiro
AU - Ueda, Toshiaki
AU - Usami, Kimiyoshi
AU - Nishio, Seiichi
AU - Murakata, Masami
AU - Mitsuhashi, Takashi
PY - 1998
Y1 - 1998
N2 - This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.
AB - This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.
UR - http://www.scopus.com/inward/record.url?scp=0032218674&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0032218674&partnerID=8YFLogxK
M3 - Chapter
SP - 307
EP - 312
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PB - IEEE
CY - Piscataway, NJ, United States
ER -