Clock-gating method for low-power LSI design

Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi

Research output: Chapter in Book/Report/Conference proceedingChapter

12 Citations (Scopus)

Abstract

This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages307-312
Number of pages6
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
Duration: 1998 Feb 101998 Feb 13

Other

OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period98/2/1098/2/13

Fingerprint

Clocks
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M., & Mitsuhashi, T. (1998). Clock-gating method for low-power LSI design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 307-312). Piscataway, NJ, United States: IEEE.

Clock-gating method for low-power LSI design. / Kitahara, Takeshi; Minami, Fumihiro; Ueda, Toshiaki; Usami, Kimiyoshi; Nishio, Seiichi; Murakata, Masami; Mitsuhashi, Takashi.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. p. 307-312.

Research output: Chapter in Book/Report/Conference proceedingChapter

Kitahara, T, Minami, F, Ueda, T, Usami, K, Nishio, S, Murakata, M & Mitsuhashi, T 1998, Clock-gating method for low-power LSI design. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, Piscataway, NJ, United States, pp. 307-312, Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn, 98/2/10.
Kitahara T, Minami F, Ueda T, Usami K, Nishio S, Murakata M et al. Clock-gating method for low-power LSI design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE. 1998. p. 307-312
Kitahara, Takeshi ; Minami, Fumihiro ; Ueda, Toshiaki ; Usami, Kimiyoshi ; Nishio, Seiichi ; Murakata, Masami ; Mitsuhashi, Takashi. / Clock-gating method for low-power LSI design. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. pp. 307-312
@inbook{15a66dc341b24d298f77efdb553d0e47,
title = "Clock-gating method for low-power LSI design",
abstract = "This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.",
author = "Takeshi Kitahara and Fumihiro Minami and Toshiaki Ueda and Kimiyoshi Usami and Seiichi Nishio and Masami Murakata and Takashi Mitsuhashi",
year = "1998",
language = "English",
pages = "307--312",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "IEEE",

}

TY - CHAP

T1 - Clock-gating method for low-power LSI design

AU - Kitahara, Takeshi

AU - Minami, Fumihiro

AU - Ueda, Toshiaki

AU - Usami, Kimiyoshi

AU - Nishio, Seiichi

AU - Murakata, Masami

AU - Mitsuhashi, Takashi

PY - 1998

Y1 - 1998

N2 - This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

AB - This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed Gated-Clock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

UR - http://www.scopus.com/inward/record.url?scp=0032218674&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032218674&partnerID=8YFLogxK

M3 - Chapter

AN - SCOPUS:0032218674

SP - 307

EP - 312

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

PB - IEEE

CY - Piscataway, NJ, United States

ER -