Clustered voltage scaling technique for low-power design

Kimiyoshi Usami; Mark Horowitz

doi:10.1145/224081.224083

Clustered voltage scaling technique for low-power design

Kimiyoshi Usami, Mark Horowitz

Research output: Contribution to conference › Paper › peer-review

335 Citations (Scopus)

Abstract

This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.

Original language	English
Pages	3-8
Number of pages	6
DOIs	https://doi.org/10.1145/224081.224083
Publication status	Published - 1995
Externally published	Yes
Event	Proceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA Duration: 1995 Apr 23 → 1995 Apr 26

Other

Other	Proceedings of the 1995 International Symposium on Low Power Design
City	Dana Point, CA, USA
Period	95/4/23 → 95/4/26

ASJC Scopus subject areas

Engineering(all)

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10.1145/224081.224083

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doi = "10.1145/224081.224083",

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AU - Horowitz, Mark

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AB - This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.

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T2 - Proceedings of the 1995 International Symposium on Low Power Design

Y2 - 23 April 1995 through 26 April 1995

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Clustered voltage scaling technique for low-power design

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