Co-analysis of signal and power integrity of 3D stacked package using flexible printed circuits

Keisuke Ikemiya, Masato Kanazawa, Toshio Sudo, Shizuaki Masuda, Yasushi Hirakawa, Kikuo Wada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three dimensionally stacked package using FFCSP (Flexible carrier Folded real Chip Size Package) has been developed as one solution of high-density DRAM module. FPC (Flexible printed circuit) was effectively utilized to construct the pads at the both top and bottom sides of PoP (package-on-package) structure. In such multi-tiered package structures, the power supply stability for the upper tiered package is estimated to be worse than that of the lower tiered package due to parasitic inductance. In this paper, the co-analysis model including signal integrity (SI) and power integrity (PI) has been established to evaluate the power supply and signal quality among the multi-tiered chips. In particular, the power distribution networks (PDN) and eye diagrams for multi-tiered package were discussed.

Original languageEnglish
Title of host publicationIEEE International Symposium on Electromagnetic Compatibility
DOIs
Publication statusPublished - 2012
EventInternational Symposium on Electromagnetic Compatibility, EMC EUROPE 2012 - Rome
Duration: 2012 Sep 172012 Sep 21

Other

OtherInternational Symposium on Electromagnetic Compatibility, EMC EUROPE 2012
CityRome
Period12/9/1712/9/21

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Ikemiya, K., Kanazawa, M., Sudo, T., Masuda, S., Hirakawa, Y., & Wada, K. (2012). Co-analysis of signal and power integrity of 3D stacked package using flexible printed circuits. In IEEE International Symposium on Electromagnetic Compatibility [6396881] https://doi.org/10.1109/EMCEurope.2012.6396881