CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.

Haruyuki Sakamoto; Eiji Watanabe; Akinori Nishihara

CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.

Haruyuki Sakamoto, Eiji Watanabe, Akinori Nishihara

Research output: Contribution to journal › Conference article › peer-review

Abstract

A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.

Original language	English
Pages (from-to)	1403-1406
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Publication status	Published - 1985 Dec 1

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.",

abstract = "A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.",

author = "Haruyuki Sakamoto and Eiji Watanabe and Akinori Nishihara",

year = "1985",

month = dec,

day = "1",

language = "English",

pages = "1403--1406",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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AU - Sakamoto, Haruyuki

AU - Watanabe, Eiji

AU - Nishihara, Akinori

PY - 1985/12/1

Y1 - 1985/12/1

N2 - A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.

AB - A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.

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M3 - Conference article

AN - SCOPUS:0022324952

SN - 0271-4310

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.

Abstract

ASJC Scopus subject areas

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