CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.

Haruyuki Sakamoto, Eiji Watanabe, Akinori Nishihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages1403-1406
Number of pages4
Publication statusPublished - 1985
Externally publishedYes

Fingerprint

Program assemblers
High level languages
Binary trees
Code generation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Sakamoto, H., Watanabe, E., & Nishihara, A. (1985). CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1403-1406). IEEE.

CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS. / Sakamoto, Haruyuki; Watanabe, Eiji; Nishihara, Akinori.

Proceedings - IEEE International Symposium on Circuits and Systems. IEEE, 1985. p. 1403-1406.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sakamoto, H, Watanabe, E & Nishihara, A 1985, CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS. in Proceedings - IEEE International Symposium on Circuits and Systems. IEEE, pp. 1403-1406.
Sakamoto H, Watanabe E, Nishihara A. CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS. In Proceedings - IEEE International Symposium on Circuits and Systems. IEEE. 1985. p. 1403-1406
Sakamoto, Haruyuki ; Watanabe, Eiji ; Nishihara, Akinori. / CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS. Proceedings - IEEE International Symposium on Circuits and Systems. IEEE, 1985. pp. 1403-1406
@inproceedings{4f5cb8dd93984373a4b6abea4d6b6f23,
title = "CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.",
abstract = "A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.",
author = "Haruyuki Sakamoto and Eiji Watanabe and Akinori Nishihara",
year = "1985",
language = "English",
pages = "1403--1406",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "IEEE",

}

TY - GEN

T1 - CODE OPTIMIZATION OF DIGITAL NETWORKS FOR SIGNAL PROCESSORS.

AU - Sakamoto, Haruyuki

AU - Watanabe, Eiji

AU - Nishihara, Akinori

PY - 1985

Y1 - 1985

N2 - A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.

AB - A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.

UR - http://www.scopus.com/inward/record.url?scp=0022324952&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022324952&partnerID=8YFLogxK

M3 - Conference contribution

SP - 1403

EP - 1406

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -