Computer-aided analysis of surface-state effects on gate-lag phenomena in GaAs MESFETs

Kazushige Horio, Tomiko Yamada

Research output: Contribution to conferencePaper

Abstract

Physical mechanism of gate-lag or slow current transient in GaAs MESFETs is studied by two-dimensional simulation including surface-state effects. It is shown that the gate-lag becomes noticeable when the deep-acceptor-like surface state acts as a hole trap. To reduce it, the deep acceptor should be made electron-trap-like, which could be realized by reducing the surface-state density. Structures expected to have less gate-lag, such as a self-aligned structure and a recessed-gate structure are also analyzed. It is physically discussed whether the gate-lag can be completely eliminated in these structures.

Original languageEnglish
Pages432-437
Number of pages6
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE'98 - Pisa, Italy
Duration: 1998 Sep 291998 Oct 2

Other

OtherProceedings of the 1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE'98
CityPisa, Italy
Period98/9/2998/10/2

ASJC Scopus subject areas

  • Signal Processing

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    Horio, K., & Yamada, T. (1998). Computer-aided analysis of surface-state effects on gate-lag phenomena in GaAs MESFETs. 432-437. Paper presented at Proceedings of the 1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE'98, Pisa, Italy, .