Considerations on package design for high speed and high pin count CMOS devices

Toshio Sudo, Toshiaki Mori, Takashi Yoshimori

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

High-speed, high-density CMOS VLSI devices have powerful output buffers to charge a load capacitance quickly, which causes large switching noise on the power/ground lines. Furthermore, the equivalent impedance of the output buffer becomes lower than the characteristic impedance of the transmission line on a board, which induces complicated phenomena, including ringing noise. These problems are discussed, and the electrical characteristics of a 348-pin QFP (quad flat package) developed for a 1-micron, 129-K gate CMOS gate array is described. The factors that determine switching noise were investigated by a simulation that represents the packaging environment. A test chip for evaluating the switching noise was designed and used to characterize the 348-pin QFP. Disagreement between measured data and simulation results remains to be investigated.

Original languageEnglish
Pages (from-to)531-538
Number of pages8
JournalProceedings - Electronic Components and Technology Conference
Publication statusPublished - 1989 Dec 1
Event39th Electronic Components - Houston, TX, USA
Duration: 1989 May 221989 May 24

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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