Abstract
A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm 2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.
| Original language | English |
|---|---|
| Title of host publication | 2011 International Conference on Field-Programmable Technology, FPT 2011 |
| DOIs | |
| Publication status | Published - 2011 |
| Event | 2011 International Conference on Field-Programmable Technology, FPT 2011 - New Delhi Duration: 2011 Dec 12 → 2011 Dec 14 |
Other
| Other | 2011 International Conference on Field-Programmable Technology, FPT 2011 |
|---|---|
| City | New Delhi |
| Period | 11/12/12 → 11/12/14 |
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ASJC Scopus subject areas
- Computational Mathematics
Cite this
Cool mega-array : A highly energy efficient reconfigurable accelerator. / Ozaki, N.; Yoshihiro, Y.; Saito, Y.; Ikebuchi, D.; Kimura, M.; Amano, H.; Nakamura, H.; Usami, Kimiyoshi; Namiki, M.; Kondo, M.
2011 International Conference on Field-Programmable Technology, FPT 2011. 2011. 6132668.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Cool mega-array
T2 - A highly energy efficient reconfigurable accelerator
AU - Ozaki, N.
AU - Yoshihiro, Y.
AU - Saito, Y.
AU - Ikebuchi, D.
AU - Kimura, M.
AU - Amano, H.
AU - Nakamura, H.
AU - Usami, Kimiyoshi
AU - Namiki, M.
AU - Kondo, M.
PY - 2011
Y1 - 2011
N2 - A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm 2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.
AB - A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm 2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.
UR - http://www.scopus.com/inward/record.url?scp=84857214326&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84857214326&partnerID=8YFLogxK
U2 - 10.1109/FPT.2011.6132668
DO - 10.1109/FPT.2011.6132668
M3 - Conference contribution
AN - SCOPUS:84857214326
SN - 9781457717406
BT - 2011 International Conference on Field-Programmable Technology, FPT 2011
ER -