Correlation of PDN impedance between measurements and simulation of 3D-SiP

Shohei Kawaguchi, Masaomi Sato, Hiroki Takatani, Yosuke Tanaka, Haruya Fujita, Yoichi Suto, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Recently, ultra-wide bus 3D-SiP with TSV's has attracted great attention to achieve energy-saving and high-performance system level module. TSV technology is a new technology of vertical wiring to make shorter than the conventional wire bonding. However, the power supply integrity and signal integrity has become an issue due to the increase of simultaneous switching output buffers. In this paper, PDN impedances of 3D-SiP were examined by the measurement and simulation. Simulated PDN impedances of three chips were well correlated with the measured results.

Original languageEnglish
Title of host publicationEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
Pages158-161
Number of pages4
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013 - Nara, Japan
Duration: 2013 Dec 122013 Dec 15

Publication series

NameEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium

Conference

Conference2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
CountryJapan
CityNara
Period13/12/1213/12/15

Keywords

  • 3D-SiP
  • measurement
  • on-die capacitance
  • power distribution network (PDN)
  • simultaneous switching noise
  • ultra-wide bus

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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