Datapath generator based on gate-level symbolic layout

Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21K-transistor data-path whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath, was generated using 1-μm CMOS technology.

Original languageEnglish
Title of host publication27th ACM/IEEE Design Automation Conference. Proceedings 1990
PublisherPubl by IEEE
Pages388-393
Number of pages6
ISBN (Print)081869650X
DOIs
Publication statusPublished - 1990
Event27th ACM/IEEE Design Automation Conference - Orlando, FL, USA
Duration: 1990 Jun 241990 Jun 28

Publication series

Name27th ACM/IEEE Design Automation Conference. Proceedings 1990

Other

Other27th ACM/IEEE Design Automation Conference
CityOrlando, FL, USA
Period90/6/2490/6/28

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H., & Mori, S. (1990). Datapath generator based on gate-level symbolic layout. In 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (pp. 388-393). (27th ACM/IEEE Design Automation Conference. Proceedings 1990). Publ by IEEE. https://doi.org/10.1145/123186.123314