Delay modeling and critical-path delay calculation for MTCMOS circuits

Naoaki Ohkubo, Kimiyoshi Usami

Research output: Contribution to journalArticle

Abstract

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8 errors compared with SPICE simulation.

Original languageEnglish
Pages (from-to)3482-3490
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE89-A
Issue number12
DOIs
Publication statusPublished - 2006 Dec

Fingerprint

Delay circuits
Networks (circuits)
Electric potential
SPICE
Interpolation
Capacitance
Switches

Keywords

  • Delay modeling
  • Leakage power
  • MTCMOS
  • Selective-MT
  • Static timing analysis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Delay modeling and critical-path delay calculation for MTCMOS circuits. / Ohkubo, Naoaki; Usami, Kimiyoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 12, 12.2006, p. 3482-3490.

Research output: Contribution to journalArticle

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