Delay modeling and static timing analysis for MTCMOS circuits

Naoaki Ohkubo, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
Pages570-575
Number of pages6
Publication statusPublished - 2006 Sep 19
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: 2006 Jan 242006 Jan 27

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2006

Conference

ConferenceASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period06/1/2406/1/27

Keywords

  • Delay
  • Interpolation
  • Leakage power
  • MTCMOS
  • Selective-MT
  • Static timing analysis

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Ohkubo, N., & Usami, K. (2006). Delay modeling and static timing analysis for MTCMOS circuits. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 570-575). [1594746] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).