Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a design and control scheme of a microprocessor whose internal function units are power gated at instruction-by-instruction basis. Enabling/disabling the power gating is adaptively controlled under the support of on-chip leakage monitors and the operating system to minimize energy overhead due to sleep-in and wakeup. Measured results of the fabricated chip in the 65nm CMOS technology demonstrated that our approach reduces energy to 21-35% in the range of 25-85°C as compared to the non power-gated case. Energy dissipation was reduced by up to 15% as compared to the conventional fine-grain power gating technique in the same temperature range.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages843-848
Number of pages6
DOIs
Publication statusPublished - 2014
Event2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec
Duration: 2014 Jan 202014 Jan 23

Other

Other2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
CitySuntec
Period14/1/2014/1/23

Fingerprint

Microprocessor chips
Energy dissipation
Temperature
Sleep

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., ... Nakamura, H. (2014). Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 843-848). [6742995] https://doi.org/10.1109/ASPDAC.2014.6742995

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. / Usami, Kimiyoshi; Kudo, Masaru; Matsunaga, Kensaku; Kosaka, Tsubasa; Tsurui, Yoshihiro; Wang, Weihan; Amano, Hideharu; Kobayashi, Hiroaki; Sakamoto, Ryuichi; Namiki, Mitaro; Kondo, Masaaki; Nakamura, Hiroshi.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 843-848 6742995.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Kudo, M, Matsunaga, K, Kosaka, T, Tsurui, Y, Wang, W, Amano, H, Kobayashi, H, Sakamoto, R, Namiki, M, Kondo, M & Nakamura, H 2014, Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 6742995, pp. 843-848, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Suntec, 14/1/20. https://doi.org/10.1109/ASPDAC.2014.6742995
Usami K, Kudo M, Matsunaga K, Kosaka T, Tsurui Y, Wang W et al. Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. p. 843-848. 6742995 https://doi.org/10.1109/ASPDAC.2014.6742995
Usami, Kimiyoshi ; Kudo, Masaru ; Matsunaga, Kensaku ; Kosaka, Tsubasa ; Tsurui, Yoshihiro ; Wang, Weihan ; Amano, Hideharu ; Kobayashi, Hiroaki ; Sakamoto, Ryuichi ; Namiki, Mitaro ; Kondo, Masaaki ; Nakamura, Hiroshi. / Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2014. pp. 843-848
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