Design and implementation fine-grained power gating on microprocessor functional units

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip . Geyser-1 has been implemented with Fujitsu's 65 nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25°C and 23% at 80°C.

Original languageEnglish
Pages (from-to)182-192
Number of pages11
JournalIPSJ Transactions on System LSI Design Methodology
Volume4
DOIs
Publication statusPublished - 2011

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Microprocessor chips
Electric power utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Design and implementation fine-grained power gating on microprocessor functional units. / Lei, Zhao; Ikebuchi, Daisuke; Usami, Kimiyoshi; Namiki, Mitaro; Kondo, Masaaki; Nakamura, Hiroshi; Amano, Hideharu.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 4, 2011, p. 182-192.

Research output: Contribution to journalArticle

Lei, Zhao ; Ikebuchi, Daisuke ; Usami, Kimiyoshi ; Namiki, Mitaro ; Kondo, Masaaki ; Nakamura, Hiroshi ; Amano, Hideharu. / Design and implementation fine-grained power gating on microprocessor functional units. In: IPSJ Transactions on System LSI Design Methodology. 2011 ; Vol. 4. pp. 182-192.
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