Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yusuke Yoshida; Kimiyoshi Usami

doi:10.1109/ULIS.2017.7962596

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yusuke Yoshida, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

Original language	English
Title of host publication	Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
Editors	Androula G. Nassiopoulou, Panagiotis Sarafis
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	43-46
Number of pages	4
ISBN (Electronic)	9781509053131
DOIs	https://doi.org/10.1109/ULIS.2017.7962596
Publication status	Published - 2017 Jun 29
Event	2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece Duration: 2017 Apr 3 → 2017 Apr 5

Publication series

Name	Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

Other

Other	2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
Country/Territory	Greece
City	Athens
Period	17/4/3 → 17/4/5

Keywords

Body bias
Energy-Efficient
Silicon-on-Thin-BOX(SOTB)
Standard Cell Memory
Ultra-low voltage

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Instrumentation
Electrical and Electronic Engineering

Access to Document

10.1109/ULIS.2017.7962596

Cite this

Yoshida, Y., & Usami, K. (2017). Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. In A. G. Nassiopoulou, & P. Sarafis (Eds.), Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings (pp. 43-46). [7962596] (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2017.7962596

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. / Yoshida, Yusuke; Usami, Kimiyoshi.

Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. ed. / Androula G. Nassiopoulou; Panagiotis Sarafis. Institute of Electrical and Electronics Engineers Inc., 2017. p. 43-46 7962596 (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshida, Y & Usami, K 2017, Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. in AG Nassiopoulou & P Sarafis (eds), Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings., 7962596, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 43-46, 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Athens, Greece, 17/4/3. https://doi.org/10.1109/ULIS.2017.7962596

Yoshida Y, Usami K. Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. In Nassiopoulou AG, Sarafis P, editors, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 43-46. 7962596. (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings). doi: 10.1109/ULIS.2017.7962596

Yoshida, Yusuke ; Usami, Kimiyoshi. / Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. editor / Androula G. Nassiopoulou ; Panagiotis Sarafis. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 43-46 (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

@inproceedings{07b5a07f1da64823abd698dfedb05840,

title = "Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX",

abstract = "This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.",

keywords = "Body bias, Energy-Efficient, Silicon-on-Thin-BOX(SOTB), Standard Cell Memory, Ultra-low voltage",

author = "Yusuke Yoshida and Kimiyoshi Usami",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 ; Conference date: 03-04-2017 Through 05-04-2017",

year = "2017",

month = jun,

day = "29",

doi = "10.1109/ULIS.2017.7962596",

language = "English",

series = "Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "43--46",

editor = "Nassiopoulou, {Androula G.} and Panagiotis Sarafis",

booktitle = "Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings",

}

TY - GEN

T1 - Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

AU - Yoshida, Yusuke

AU - Usami, Kimiyoshi

PY - 2017/6/29

Y1 - 2017/6/29

N2 - This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

AB - This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

KW - Body bias

KW - Energy-Efficient

KW - Silicon-on-Thin-BOX(SOTB)

KW - Standard Cell Memory

KW - Ultra-low voltage

UR - http://www.scopus.com/inward/record.url?scp=85026787209&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85026787209&partnerID=8YFLogxK

U2 - 10.1109/ULIS.2017.7962596

DO - 10.1109/ULIS.2017.7962596

M3 - Conference contribution

AN - SCOPUS:85026787209

T3 - Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

SP - 43

EP - 46

BT - Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

A2 - Nassiopoulou, Androula G.

A2 - Sarafis, Panagiotis

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017

Y2 - 3 April 2017 through 5 April 2017

ER -

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

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