Abstract
This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.
Original language | English |
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Title of host publication | Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 43-46 |
Number of pages | 4 |
ISBN (Electronic) | 9781509053131 |
DOIs | |
Publication status | Published - 2017 Jun 29 |
Event | 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece Duration: 2017 Apr 3 → 2017 Apr 5 |
Other
Other | 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 |
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Country | Greece |
City | Athens |
Period | 17/4/3 → 17/4/5 |
Keywords
- Body bias
- Energy-Efficient
- Silicon-on-Thin-BOX(SOTB)
- Standard Cell Memory
- Ultra-low voltage
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Instrumentation
- Electrical and Electronic Engineering