Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yusuke Yoshida, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Citations

Abstract

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

LanguageEnglish
Title of host publicationJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages43-46
Number of pages4
ISBN (Electronic)9781509053131
DOIs
StatePublished - 2017 Jun 29
Event2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece
Duration: 2017 Apr 32017 Apr 5

Other

Other2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
CountryGreece
CityAthens
Period17/4/317/4/5

Fingerprint

Silicon
methodology
Data storage equipment
silicon
cells
energy
latches
Computer peripheral equipment
Flip flop circuits
electric potential
Bias voltage
clocks
Clocks
Energy dissipation
leakage
energy dissipation
Networks (circuits)
Electric potential
simulation

Keywords

  • Body bias
  • Energy-Efficient
  • Silicon-on-Thin-BOX(SOTB)
  • Standard Cell Memory
  • Ultra-low voltage

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Yoshida, Y., & Usami, K. (2017). Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. In Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings (pp. 43-46). [7962596] Institute of Electrical and Electronics Engineers Inc.. DOI: 10.1109/ULIS.2017.7962596

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. / Yoshida, Yusuke; Usami, Kimiyoshi.

Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 43-46 7962596.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshida, Y & Usami, K 2017, Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. in Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings., 7962596, Institute of Electrical and Electronics Engineers Inc., pp. 43-46, 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Athens, Greece, 17/4/3. DOI: 10.1109/ULIS.2017.7962596
Yoshida Y, Usami K. Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. In Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc.2017. p. 43-46. 7962596. Available from, DOI: 10.1109/ULIS.2017.7962596
Yoshida, Yusuke ; Usami, Kimiyoshi. / Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 43-46
@inproceedings{07b5a07f1da64823abd698dfedb05840,
title = "Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX",
abstract = "This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40{\%} smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70{\%} smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.",
keywords = "Body bias, Energy-Efficient, Silicon-on-Thin-BOX(SOTB), Standard Cell Memory, Ultra-low voltage",
author = "Yusuke Yoshida and Kimiyoshi Usami",
year = "2017",
month = "6",
day = "29",
doi = "10.1109/ULIS.2017.7962596",
language = "English",
pages = "43--46",
booktitle = "Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

AU - Yoshida,Yusuke

AU - Usami,Kimiyoshi

PY - 2017/6/29

Y1 - 2017/6/29

N2 - This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

AB - This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

KW - Body bias

KW - Energy-Efficient

KW - Silicon-on-Thin-BOX(SOTB)

KW - Standard Cell Memory

KW - Ultra-low voltage

UR - http://www.scopus.com/inward/record.url?scp=85026787209&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85026787209&partnerID=8YFLogxK

U2 - 10.1109/ULIS.2017.7962596

DO - 10.1109/ULIS.2017.7962596

M3 - Conference contribution

SP - 43

EP - 46

BT - Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -