Abstract
This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.
| Language | English |
|---|---|
| Title of host publication | Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 43-46 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781509053131 |
| DOIs | |
| State | Published - 2017 Jun 29 |
| Event | 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece Duration: 2017 Apr 3 → 2017 Apr 5 |
Other
| Other | 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 |
|---|---|
| Country | Greece |
| City | Athens |
| Period | 17/4/3 → 17/4/5 |
Fingerprint
Keywords
- Body bias
- Energy-Efficient
- Silicon-on-Thin-BOX(SOTB)
- Standard Cell Memory
- Ultra-low voltage
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Instrumentation
- Electrical and Electronic Engineering
Cite this
Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. / Yoshida, Yusuke; Usami, Kimiyoshi.
Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 43-46 7962596.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX
AU - Yoshida,Yusuke
AU - Usami,Kimiyoshi
PY - 2017/6/29
Y1 - 2017/6/29
N2 - This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.
AB - This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.
KW - Body bias
KW - Energy-Efficient
KW - Silicon-on-Thin-BOX(SOTB)
KW - Standard Cell Memory
KW - Ultra-low voltage
UR - http://www.scopus.com/inward/record.url?scp=85026787209&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85026787209&partnerID=8YFLogxK
U2 - 10.1109/ULIS.2017.7962596
DO - 10.1109/ULIS.2017.7962596
M3 - Conference contribution
SP - 43
EP - 46
BT - Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -