Design and implementation of fine-grain power gating with ground bounce suppression

Kimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Abstract

This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement makes suppression of the ground-bounce more difficult. We propose a novel technique to skew the wakeup timings of fine-grain local power domains to suppress the ground bounce. Delay of buffers driving power switches is skewed in the buffer tree by selectively downsizing them. We designed a MIPS R3000 based CPU core in a 90nm CMOS technology and applied our technique to internal function units. Simulation results showed that our technique reduces the rush current to 47% over the case to turn-on the power switches simultaneously. This resulted in suppressing the ground bounce to 53mV with 3.3ns wakeup time. Simulation results from running benchmark programs showed that the total power dissipation for the function units was reduced by up to 15% at 25°C and by 62% at 100°C. Effectiveness in power savings is discussed from the viewpoint of the temperature-dependent break-even points and the consecutive idle time in the program.

Original languageEnglish
Title of host publicationProceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Pages381-386
Number of pages6
DOIs
Publication statusPublished - 2009
Event22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems - New Delhi
Duration: 2009 Jan 52009 Jan 9

Other

Other22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
CityNew Delhi
Period09/1/509/1/9

Fingerprint

Switches
Program processors
Energy dissipation
Temperature
Sleep

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., ... Nakamura, H. (2009). Design and implementation of fine-grain power gating with ground bounce suppression. In Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems (pp. 381-386). [4749703] https://doi.org/10.1109/VLSI.Design.2009.63

Design and implementation of fine-grain power gating with ground bounce suppression. / Usami, Kimiyoshi; Shirai, Toshiaki; Hashida, Tasunori; Masuda, Hiroki; Takeda, Seidai; Nakata, Mitsutaka; Seki, Naomi; Amano, Hideharu; Namiki, Mitaro; Imai, Masashi; Kondo, Masaaki; Nakamura, Hiroshi.

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. p. 381-386 4749703.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Shirai, T, Hashida, T, Masuda, H, Takeda, S, Nakata, M, Seki, N, Amano, H, Namiki, M, Imai, M, Kondo, M & Nakamura, H 2009, Design and implementation of fine-grain power gating with ground bounce suppression. in Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems., 4749703, pp. 381-386, 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems, New Delhi, 09/1/5. https://doi.org/10.1109/VLSI.Design.2009.63
Usami K, Shirai T, Hashida T, Masuda H, Takeda S, Nakata M et al. Design and implementation of fine-grain power gating with ground bounce suppression. In Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. p. 381-386. 4749703 https://doi.org/10.1109/VLSI.Design.2009.63
Usami, Kimiyoshi ; Shirai, Toshiaki ; Hashida, Tasunori ; Masuda, Hiroki ; Takeda, Seidai ; Nakata, Mitsutaka ; Seki, Naomi ; Amano, Hideharu ; Namiki, Mitaro ; Imai, Masashi ; Kondo, Masaaki ; Nakamura, Hiroshi. / Design and implementation of fine-grain power gating with ground bounce suppression. Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. pp. 381-386
@inproceedings{636e70c4035f4892aef13264e0b9cce2,
title = "Design and implementation of fine-grain power gating with ground bounce suppression",
abstract = "This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement makes suppression of the ground-bounce more difficult. We propose a novel technique to skew the wakeup timings of fine-grain local power domains to suppress the ground bounce. Delay of buffers driving power switches is skewed in the buffer tree by selectively downsizing them. We designed a MIPS R3000 based CPU core in a 90nm CMOS technology and applied our technique to internal function units. Simulation results showed that our technique reduces the rush current to 47{\%} over the case to turn-on the power switches simultaneously. This resulted in suppressing the ground bounce to 53mV with 3.3ns wakeup time. Simulation results from running benchmark programs showed that the total power dissipation for the function units was reduced by up to 15{\%} at 25°C and by 62{\%} at 100°C. Effectiveness in power savings is discussed from the viewpoint of the temperature-dependent break-even points and the consecutive idle time in the program.",
author = "Kimiyoshi Usami and Toshiaki Shirai and Tasunori Hashida and Hiroki Masuda and Seidai Takeda and Mitsutaka Nakata and Naomi Seki and Hideharu Amano and Mitaro Namiki and Masashi Imai and Masaaki Kondo and Hiroshi Nakamura",
year = "2009",
doi = "10.1109/VLSI.Design.2009.63",
language = "English",
isbn = "9780769535067",
pages = "381--386",
booktitle = "Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems",

}

TY - GEN

T1 - Design and implementation of fine-grain power gating with ground bounce suppression

AU - Usami, Kimiyoshi

AU - Shirai, Toshiaki

AU - Hashida, Tasunori

AU - Masuda, Hiroki

AU - Takeda, Seidai

AU - Nakata, Mitsutaka

AU - Seki, Naomi

AU - Amano, Hideharu

AU - Namiki, Mitaro

AU - Imai, Masashi

AU - Kondo, Masaaki

AU - Nakamura, Hiroshi

PY - 2009

Y1 - 2009

N2 - This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement makes suppression of the ground-bounce more difficult. We propose a novel technique to skew the wakeup timings of fine-grain local power domains to suppress the ground bounce. Delay of buffers driving power switches is skewed in the buffer tree by selectively downsizing them. We designed a MIPS R3000 based CPU core in a 90nm CMOS technology and applied our technique to internal function units. Simulation results showed that our technique reduces the rush current to 47% over the case to turn-on the power switches simultaneously. This resulted in suppressing the ground bounce to 53mV with 3.3ns wakeup time. Simulation results from running benchmark programs showed that the total power dissipation for the function units was reduced by up to 15% at 25°C and by 62% at 100°C. Effectiveness in power savings is discussed from the viewpoint of the temperature-dependent break-even points and the consecutive idle time in the program.

AB - This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement makes suppression of the ground-bounce more difficult. We propose a novel technique to skew the wakeup timings of fine-grain local power domains to suppress the ground bounce. Delay of buffers driving power switches is skewed in the buffer tree by selectively downsizing them. We designed a MIPS R3000 based CPU core in a 90nm CMOS technology and applied our technique to internal function units. Simulation results showed that our technique reduces the rush current to 47% over the case to turn-on the power switches simultaneously. This resulted in suppressing the ground bounce to 53mV with 3.3ns wakeup time. Simulation results from running benchmark programs showed that the total power dissipation for the function units was reduced by up to 15% at 25°C and by 62% at 100°C. Effectiveness in power savings is discussed from the viewpoint of the temperature-dependent break-even points and the consecutive idle time in the program.

UR - http://www.scopus.com/inward/record.url?scp=62949189195&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62949189195&partnerID=8YFLogxK

U2 - 10.1109/VLSI.Design.2009.63

DO - 10.1109/VLSI.Design.2009.63

M3 - Conference contribution

AN - SCOPUS:62949189195

SN - 9780769535067

SP - 381

EP - 386

BT - Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

ER -