Design of a 32bit microprocessor, TX1

Takeji Tokumaru; Eiji Masuda; Chikahiro Hori; Kimiyoshi Usami; Misao Miyata; Jun Iwamura

Design of a 32bit microprocessor, TX1

Takeji Tokumaru, Eiji Masuda, Chikahiro Hori, Kimiyoshi Usami, Misao Miyata, Jun Iwamura

Research output: Contribution to conference › Paper › peer-review

Abstract

TX1 is a 32-bit microprocessor of the Toshiba TX series of microprocessors, which are fully based on the TRON architecture. TX1 supports 88 instructions and executes basic instructions in 2 cycles at 25 MHz. The average performance of TX1 is more than 5 MIPS. Implementation of the TX1 is described. Particular emphasis is placed on a design style suitable for VLSI microprocessors including full utilization of design automation such as logic synthesis and automatic place and router. The clock skew problem is also studied and successfully resolved.

Original language	English
Pages	33-34
Number of pages	2
Publication status	Published - 1988 Dec 1
Externally published	Yes
Event	1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan Duration: 1988 Aug 22 → 1988 Aug 24

Other

Other	1988 Symposium on VLSI Circuits - Digest of Technical Papers
City	Tokyo, Japan
Period	88/8/22 → 88/8/24

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "Design of a 32bit microprocessor, TX1",

abstract = "TX1 is a 32-bit microprocessor of the Toshiba TX series of microprocessors, which are fully based on the TRON architecture. TX1 supports 88 instructions and executes basic instructions in 2 cycles at 25 MHz. The average performance of TX1 is more than 5 MIPS. Implementation of the TX1 is described. Particular emphasis is placed on a design style suitable for VLSI microprocessors including full utilization of design automation such as logic synthesis and automatic place and router. The clock skew problem is also studied and successfully resolved.",

author = "Takeji Tokumaru and Eiji Masuda and Chikahiro Hori and Kimiyoshi Usami and Misao Miyata and Jun Iwamura",

year = "1988",

month = dec,

day = "1",

language = "English",

pages = "33--34",

note = "1988 Symposium on VLSI Circuits - Digest of Technical Papers ; Conference date: 22-08-1988 Through 24-08-1988",

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T1 - Design of a 32bit microprocessor, TX1

AU - Tokumaru, Takeji

AU - Masuda, Eiji

AU - Hori, Chikahiro

AU - Usami, Kimiyoshi

AU - Miyata, Misao

AU - Iwamura, Jun

PY - 1988/12/1

Y1 - 1988/12/1

N2 - TX1 is a 32-bit microprocessor of the Toshiba TX series of microprocessors, which are fully based on the TRON architecture. TX1 supports 88 instructions and executes basic instructions in 2 cycles at 25 MHz. The average performance of TX1 is more than 5 MIPS. Implementation of the TX1 is described. Particular emphasis is placed on a design style suitable for VLSI microprocessors including full utilization of design automation such as logic synthesis and automatic place and router. The clock skew problem is also studied and successfully resolved.

AB - TX1 is a 32-bit microprocessor of the Toshiba TX series of microprocessors, which are fully based on the TRON architecture. TX1 supports 88 instructions and executes basic instructions in 2 cycles at 25 MHz. The average performance of TX1 is more than 5 MIPS. Implementation of the TX1 is described. Particular emphasis is placed on a design style suitable for VLSI microprocessors including full utilization of design automation such as logic synthesis and automatic place and router. The clock skew problem is also studied and successfully resolved.

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M3 - Paper

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T2 - 1988 Symposium on VLSI Circuits - Digest of Technical Papers

Y2 - 22 August 1988 through 24 August 1988

ER -

Design of a 32bit microprocessor, TX1

Abstract

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ASJC Scopus subject areas

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