Design Optimization of Wiring Substrate for a CMOS-Based Multichip Module,

T.Sudo T.Sudo, N.Hirano N.Hirano, K.Kato K.Kato, Y.Hiruta Y.Hiruta, Y.Fuchida Y.Fuchida, Toshio Sudo

Research output: Contribution to journalArticle

1 Citation (Scopus)
Original languageEnglish
Pages (from-to)710-716
JournalECTC
Publication statusPublished - 1992 May 25

Cite this

T.Sudo, T. S., N.Hirano, N. H., K.Kato, K. K., Y.Hiruta, Y. H., Y.Fuchida, Y. F., & Sudo, T. (1992). Design Optimization of Wiring Substrate for a CMOS-Based Multichip Module, ECTC, 710-716.

Design Optimization of Wiring Substrate for a CMOS-Based Multichip Module, / T.Sudo, T.Sudo; N.Hirano, N.Hirano; K.Kato, K.Kato; Y.Hiruta, Y.Hiruta; Y.Fuchida, Y.Fuchida; Sudo, Toshio.

In: ECTC, 25.05.1992, p. 710-716.

Research output: Contribution to journalArticle

T.Sudo, TS, N.Hirano, NH, K.Kato, KK, Y.Hiruta, YH, Y.Fuchida, YF & Sudo, T 1992, 'Design Optimization of Wiring Substrate for a CMOS-Based Multichip Module,', ECTC, pp. 710-716.
T.Sudo TS, N.Hirano NH, K.Kato KK, Y.Hiruta YH, Y.Fuchida YF, Sudo T. Design Optimization of Wiring Substrate for a CMOS-Based Multichip Module, ECTC. 1992 May 25;710-716.
T.Sudo, T.Sudo ; N.Hirano, N.Hirano ; K.Kato, K.Kato ; Y.Hiruta, Y.Hiruta ; Y.Fuchida, Y.Fuchida ; Sudo, Toshio. / Design Optimization of Wiring Substrate for a CMOS-Based Multichip Module,. In: ECTC. 1992 ; pp. 710-716.
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