Design optimization of wiring substrate in a CMOS-based multichip module

Toshio Sudo, Naohiko Hirano, Katsuto Kato, Youichi Hiruta, Yumi Fuchida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Both line resistance and RC values for MCMs (multichip modules) have been found to be located in the medium position between that of LSIs and PWBs (printed wiring boards). This leads to a tradeoff between process design and output buffer design. The effects of line resistance on the electrical performance in CMOS-based MCMs are described. Switching noise, ringing noise, interconnect delay, and crosstalk noise in the line resistance range of a thin-film wiring substrate are discussed. Signal line resistance works as a damping resistor both for switching noise and for signal ringing noise. There are optimum damping conditions. The chip-to-chip delay was not substantially influenced by the line resistance as long as the line length was kept short. The line resistance, i.e., the characteristic impedance, as well as the line resistance has an important role in determining the signal propagation properties whether it behaves like an RC delay or it is in the region of the time of flight. The design of the wiring substrate must be optimized for CMOS buffer drivability to have good electrical properties and not to impose excessive requirements on thin-film process technology.

Original languageEnglish
Title of host publicationProceedings - Electronic Components Conference
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages710-716
Number of pages7
ISBN (Print)0818626607
Publication statusPublished - 1992 Jan
EventProceedings of the 42nd Electronic Components and Technology Conference - San Diego, CA, USA
Duration: 1992 May 181992 May 20

Other

OtherProceedings of the 42nd Electronic Components and Technology Conference
CitySan Diego, CA, USA
Period92/5/1892/5/20

Fingerprint

Multichip modules
Electric wiring
Damping
Thin films
Substrates
Crosstalk
Printed circuit boards
Resistors
Process design
Electric properties
Design optimization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sudo, T., Hirano, N., Kato, K., Hiruta, Y., & Fuchida, Y. (1992). Design optimization of wiring substrate in a CMOS-based multichip module. In Proceedings - Electronic Components Conference (pp. 710-716). Piscataway, NJ, United States: Publ by IEEE.

Design optimization of wiring substrate in a CMOS-based multichip module. / Sudo, Toshio; Hirano, Naohiko; Kato, Katsuto; Hiruta, Youichi; Fuchida, Yumi.

Proceedings - Electronic Components Conference. Piscataway, NJ, United States : Publ by IEEE, 1992. p. 710-716.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sudo, T, Hirano, N, Kato, K, Hiruta, Y & Fuchida, Y 1992, Design optimization of wiring substrate in a CMOS-based multichip module. in Proceedings - Electronic Components Conference. Publ by IEEE, Piscataway, NJ, United States, pp. 710-716, Proceedings of the 42nd Electronic Components and Technology Conference, San Diego, CA, USA, 92/5/18.
Sudo T, Hirano N, Kato K, Hiruta Y, Fuchida Y. Design optimization of wiring substrate in a CMOS-based multichip module. In Proceedings - Electronic Components Conference. Piscataway, NJ, United States: Publ by IEEE. 1992. p. 710-716
Sudo, Toshio ; Hirano, Naohiko ; Kato, Katsuto ; Hiruta, Youichi ; Fuchida, Yumi. / Design optimization of wiring substrate in a CMOS-based multichip module. Proceedings - Electronic Components Conference. Piscataway, NJ, United States : Publ by IEEE, 1992. pp. 710-716
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