Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages148-149
Number of pages2
ISBN (Electronic)9781538622858
DOIs
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

Fingerprint

Data storage equipment
Macros
Computer peripheral equipment
Flip flop circuits
Static random access storage
Silicon
Bias voltage
Voltage scaling
Networks (circuits)
Electric potential

Keywords

  • Body bias control
  • Low-power
  • Silicon-on-Thin-BOX (SOTB)
  • Standard cell memory
  • Ultra-low voltage

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Yoshida, Y., Usami, K., & Amano, H. (2018). Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 148-149). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368840

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. / Yoshida, Yusuke; Usami, Kimiyoshi; Amano, Hideharu.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 148-149.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshida, Y, Usami, K & Amano, H 2018, Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., pp. 148-149, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368840
Yoshida Y, Usami K, Amano H. Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. In Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 148-149 https://doi.org/10.1109/ISOCC.2017.8368840
Yoshida, Yusuke ; Usami, Kimiyoshi ; Amano, Hideharu. / Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 148-149
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