DIGITAL TELETEXT EQUALIZER LEADING TO CIRCUIT INTEGRATION.

Kazuo Ohzeki, Junzo Murakami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The design philosophy for a time-division teletext equalizer, that is compact and suitable for circuit integration is proposed. Except for a 17-kilobit RAM for an input waveform memory and a 4. 2-kbit ROM for control signals, the equalizer can be realized with 3000 logic gates. Input offset causes tap weight offset and then causes output bending at the beginning and the end of the teletext signal packet. This phenomenon, which is characteristic of a teletext equalizer, must be prevented. An analysis shows that input level-shift is more effective than output level-shift, and that an input level-shift circuit alone suffices. A breadboard model of a teletext equalizer has been constructed. This equalizer has shown excellent performance.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages1575-1581
Number of pages7
Publication statusPublished - 1984
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Ohzeki, K., & Murakami, J. (1984). DIGITAL TELETEXT EQUALIZER LEADING TO CIRCUIT INTEGRATION. In Unknown Host Publication Title (pp. 1575-1581). IEEE.