Dynamic sleep control for finite-state-machines to reduce active leakage power

Kimiyoshi Usami, Hiroshi Yoshioka

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Leakage power is predicted to become dominant in the total operation power as the transistor technology gets advanced. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125°C, is facing at difficulties such as throughput degradation or thermal runaway due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel approach to make use of an enable signal of a gated-clock technique for reducing active leakage power. A sleep transistor is provided between combinational logic circuits and the ground, and is controlled by the enable signal. When state transitions do not occur in Finite-State-Machines (FSM's), the enable signal becomes low and the state flip-flops keep the data. At the same time, the sleep transistor is turned off so that combinational logic gates are electrically disconnected from the ground to reduce leakage. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.18 μm technology. The total power was reduced by 20% at the maximum at 125°C. It was also found that performance degradation was tolerable for burn-in testing.

Original languageEnglish
Pages (from-to)3116-3123
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE87-A
Issue number12
Publication statusPublished - 2004 Dec

Fingerprint

Finite automata
Transistors
Degradation
Combinatorial circuits
Logic gates
Flip flop circuits
Logic circuits
Testing
Clocks
Throughput
Sleep
Temperature

Keywords

  • Active leakage
  • Burn-in
  • Leakage power
  • MTCMOS
  • Scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Dynamic sleep control for finite-state-machines to reduce active leakage power. / Usami, Kimiyoshi; Yoshioka, Hiroshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 12, 12.2004, p. 3116-3123.

Research output: Contribution to journalArticle

@article{4fea7e435b1b4b8798975e9eaaa23b12,
title = "Dynamic sleep control for finite-state-machines to reduce active leakage power",
abstract = "Leakage power is predicted to become dominant in the total operation power as the transistor technology gets advanced. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125°C, is facing at difficulties such as throughput degradation or thermal runaway due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel approach to make use of an enable signal of a gated-clock technique for reducing active leakage power. A sleep transistor is provided between combinational logic circuits and the ground, and is controlled by the enable signal. When state transitions do not occur in Finite-State-Machines (FSM's), the enable signal becomes low and the state flip-flops keep the data. At the same time, the sleep transistor is turned off so that combinational logic gates are electrically disconnected from the ground to reduce leakage. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60{\%} in 0.18 μm technology. The total power was reduced by 20{\%} at the maximum at 125°C. It was also found that performance degradation was tolerable for burn-in testing.",
keywords = "Active leakage, Burn-in, Leakage power, MTCMOS, Scaling",
author = "Kimiyoshi Usami and Hiroshi Yoshioka",
year = "2004",
month = "12",
language = "English",
volume = "E87-A",
pages = "3116--3123",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Dynamic sleep control for finite-state-machines to reduce active leakage power

AU - Usami, Kimiyoshi

AU - Yoshioka, Hiroshi

PY - 2004/12

Y1 - 2004/12

N2 - Leakage power is predicted to become dominant in the total operation power as the transistor technology gets advanced. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125°C, is facing at difficulties such as throughput degradation or thermal runaway due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel approach to make use of an enable signal of a gated-clock technique for reducing active leakage power. A sleep transistor is provided between combinational logic circuits and the ground, and is controlled by the enable signal. When state transitions do not occur in Finite-State-Machines (FSM's), the enable signal becomes low and the state flip-flops keep the data. At the same time, the sleep transistor is turned off so that combinational logic gates are electrically disconnected from the ground to reduce leakage. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.18 μm technology. The total power was reduced by 20% at the maximum at 125°C. It was also found that performance degradation was tolerable for burn-in testing.

AB - Leakage power is predicted to become dominant in the total operation power as the transistor technology gets advanced. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125°C, is facing at difficulties such as throughput degradation or thermal runaway due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel approach to make use of an enable signal of a gated-clock technique for reducing active leakage power. A sleep transistor is provided between combinational logic circuits and the ground, and is controlled by the enable signal. When state transitions do not occur in Finite-State-Machines (FSM's), the enable signal becomes low and the state flip-flops keep the data. At the same time, the sleep transistor is turned off so that combinational logic gates are electrically disconnected from the ground to reduce leakage. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.18 μm technology. The total power was reduced by 20% at the maximum at 125°C. It was also found that performance degradation was tolerable for burn-in testing.

KW - Active leakage

KW - Burn-in

KW - Leakage power

KW - MTCMOS

KW - Scaling

UR - http://www.scopus.com/inward/record.url?scp=11144290682&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=11144290682&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:11144290682

VL - E87-A

SP - 3116

EP - 3123

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -