Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Tatsuya Yamamoto; Kazuei Hironaka; Yuki Hayakawa; Masayuki Kimura; Hideharu Amano; Kimiyoshi Usami

doi:10.1007/978-3-642-19475-7_24

Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper describes a dynamic V_DD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower V_DD. We propose a mapping optimization algorithm "PFCM" to minimize the overhead. PFCM reduced energy overhead by 90.8% and thereby the dynamic V_DD switching technique reduced energy dissipation by up to 12.5% when running sepia filter, alpha blender and Laplacian filter programs.

Original language	English
Title of host publication	Reconfigurable Computing
Subtitle of host publication	Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings
Pages	230-241
Number of pages	12
DOIs	https://doi.org/10.1007/978-3-642-19475-7_24
Publication status	Published - 2011
Event	7th International Symposium on Applied Reconfigurable Computing, ARC 2011 - Belfast, United Kingdom Duration: 2011 Mar 23 → 2011 Mar 25

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	6578 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	7th International Symposium on Applied Reconfigurable Computing, ARC 2011
Country/Territory	United Kingdom
City	Belfast
Period	11/3/23 → 11/3/25

Keywords

Dynamic V Switching
Dynamically Reconfigurable Processor
Mapping Optimization
Power Reduction

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-642-19475-7_24

Cite this

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H., & Usami, K. (2011). Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction. In Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings (pp. 230-241). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6578 LNCS). https://doi.org/10.1007/978-3-642-19475-7_24

Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction. / Yamamoto, Tatsuya; Hironaka, Kazuei; Hayakawa, Yuki; Kimura, Masayuki; Amano, Hideharu; Usami, Kimiyoshi.

Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. 2011. p. 230-241 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6578 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yamamoto, T, Hironaka, K, Hayakawa, Y, Kimura, M, Amano, H & Usami, K 2011, Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction. in Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 6578 LNCS, pp. 230-241, 7th International Symposium on Applied Reconfigurable Computing, ARC 2011, Belfast, United Kingdom, 11/3/23. https://doi.org/10.1007/978-3-642-19475-7_24

Yamamoto T, Hironaka K, Hayakawa Y, Kimura M, Amano H, Usami K. Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction. In Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. 2011. p. 230-241. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). https://doi.org/10.1007/978-3-642-19475-7_24

Yamamoto, Tatsuya ; Hironaka, Kazuei ; Hayakawa, Yuki ; Kimura, Masayuki ; Amano, Hideharu ; Usami, Kimiyoshi. / Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction. Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. 2011. pp. 230-241 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{4092138b3a3f425d8ee4c47d858e3b44,

title = "Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction",

abstract = "This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower VDD. We propose a mapping optimization algorithm {"}PFCM{"} to minimize the overhead. PFCM reduced energy overhead by 90.8% and thereby the dynamic VDD switching technique reduced energy dissipation by up to 12.5% when running sepia filter, alpha blender and Laplacian filter programs.",

keywords = "Dynamic V Switching, Dynamically Reconfigurable Processor, Mapping Optimization, Power Reduction",

author = "Tatsuya Yamamoto and Kazuei Hironaka and Yuki Hayakawa and Masayuki Kimura and Hideharu Amano and Kimiyoshi Usami",

year = "2011",

doi = "10.1007/978-3-642-19475-7_24",

language = "English",

isbn = "9783642194740",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "230--241",

booktitle = "Reconfigurable Computing",

}

TY - GEN

T1 - Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

AU - Yamamoto, Tatsuya

AU - Hironaka, Kazuei

AU - Hayakawa, Yuki

AU - Kimura, Masayuki

AU - Amano, Hideharu

AU - Usami, Kimiyoshi

PY - 2011

Y1 - 2011

N2 - This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower VDD. We propose a mapping optimization algorithm "PFCM" to minimize the overhead. PFCM reduced energy overhead by 90.8% and thereby the dynamic VDD switching technique reduced energy dissipation by up to 12.5% when running sepia filter, alpha blender and Laplacian filter programs.

AB - This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower VDD. We propose a mapping optimization algorithm "PFCM" to minimize the overhead. PFCM reduced energy overhead by 90.8% and thereby the dynamic VDD switching technique reduced energy dissipation by up to 12.5% when running sepia filter, alpha blender and Laplacian filter programs.

KW - Dynamic V Switching

KW - Dynamically Reconfigurable Processor

KW - Mapping Optimization

KW - Power Reduction

UR - http://www.scopus.com/inward/record.url?scp=79953188709&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79953188709&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-19475-7_24

DO - 10.1007/978-3-642-19475-7_24

M3 - Conference contribution

AN - SCOPUS:79953188709

SN - 9783642194740

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 230

EP - 241

BT - Reconfigurable Computing

T2 - 7th International Symposium on Applied Reconfigurable Computing, ARC 2011

Y2 - 23 March 2011 through 25 March 2011

ER -