Effects of critically damped total PDN impedance in chip-package-board co-design

Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Tatsuya Mido, Yoshinori Kobayashi, Hideyuki Fujii, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.

Original languageEnglish
Title of host publicationIEEE International Symposium on Electromagnetic Compatibility
Pages538-543
Number of pages6
DOIs
Publication statusPublished - 2012
Event2012 IEEE International Symposium on Electromagnetic Compatibility, EMC 2012 - Pittsburgh, PA
Duration: 2012 Aug 52012 Aug 10

Other

Other2012 IEEE International Symposium on Electromagnetic Compatibility, EMC 2012
CityPittsburgh, PA
Period12/8/512/8/10

Fingerprint

Electric power distribution
power supplies
chips
impedance
Damping
integrity
damping
Logic circuits
Signal interference
logic circuits
digital electronics
Inductance
Electromagnetic waves
large scale integration
electromagnetic interference
Clocks
Capacitance
inductance
clocks
CMOS

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Kobayashi, R., Kubo, G., Otsuka, H., Mido, T., Kobayashi, Y., Fujii, H., & Sudo, T. (2012). Effects of critically damped total PDN impedance in chip-package-board co-design. In IEEE International Symposium on Electromagnetic Compatibility (pp. 538-543). [6351674] https://doi.org/10.1109/ISEMC.2012.6351674

Effects of critically damped total PDN impedance in chip-package-board co-design. / Kobayashi, Ryota; Kubo, Genki; Otsuka, Hiroki; Mido, Tatsuya; Kobayashi, Yoshinori; Fujii, Hideyuki; Sudo, Toshio.

IEEE International Symposium on Electromagnetic Compatibility. 2012. p. 538-543 6351674.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kobayashi, R, Kubo, G, Otsuka, H, Mido, T, Kobayashi, Y, Fujii, H & Sudo, T 2012, Effects of critically damped total PDN impedance in chip-package-board co-design. in IEEE International Symposium on Electromagnetic Compatibility., 6351674, pp. 538-543, 2012 IEEE International Symposium on Electromagnetic Compatibility, EMC 2012, Pittsburgh, PA, 12/8/5. https://doi.org/10.1109/ISEMC.2012.6351674
Kobayashi R, Kubo G, Otsuka H, Mido T, Kobayashi Y, Fujii H et al. Effects of critically damped total PDN impedance in chip-package-board co-design. In IEEE International Symposium on Electromagnetic Compatibility. 2012. p. 538-543. 6351674 https://doi.org/10.1109/ISEMC.2012.6351674
Kobayashi, Ryota ; Kubo, Genki ; Otsuka, Hiroki ; Mido, Tatsuya ; Kobayashi, Yoshinori ; Fujii, Hideyuki ; Sudo, Toshio. / Effects of critically damped total PDN impedance in chip-package-board co-design. IEEE International Symposium on Electromagnetic Compatibility. 2012. pp. 538-543
@inproceedings{de1423a22d924899b5d112a42434a29f,
title = "Effects of critically damped total PDN impedance in chip-package-board co-design",
abstract = "As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.",
author = "Ryota Kobayashi and Genki Kubo and Hiroki Otsuka and Tatsuya Mido and Yoshinori Kobayashi and Hideyuki Fujii and Toshio Sudo",
year = "2012",
doi = "10.1109/ISEMC.2012.6351674",
language = "English",
isbn = "9781467320610",
pages = "538--543",
booktitle = "IEEE International Symposium on Electromagnetic Compatibility",

}

TY - GEN

T1 - Effects of critically damped total PDN impedance in chip-package-board co-design

AU - Kobayashi, Ryota

AU - Kubo, Genki

AU - Otsuka, Hiroki

AU - Mido, Tatsuya

AU - Kobayashi, Yoshinori

AU - Fujii, Hideyuki

AU - Sudo, Toshio

PY - 2012

Y1 - 2012

N2 - As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.

AB - As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.

UR - http://www.scopus.com/inward/record.url?scp=84870655575&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84870655575&partnerID=8YFLogxK

U2 - 10.1109/ISEMC.2012.6351674

DO - 10.1109/ISEMC.2012.6351674

M3 - Conference contribution

SN - 9781467320610

SP - 538

EP - 543

BT - IEEE International Symposium on Electromagnetic Compatibility

ER -