Electrical design and characterization of Si interposer for system-in-package (SiP)

Shinobu Kato; Tomoyuki Tango; Kiyohisa Hasegawa; Ramesh K. Bhandari; Atsushi Sakai; Hiroshi Segawa; Takashi Kariya; Toshio Sudo

doi:10.1109/ECTC.2009.5074236

Electrical design and characterization of Si interposer for system-in-package (SiP)

Shinobu Kato, Tomoyuki Tango, Kiyohisa Hasegawa, Ramesh K. Bhandari, Atsushi Sakai, Hiroshi Segawa, Takashi Kariya, Toshio Sudo

Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

Si interposer technology has the potential to enable highbandwidth and low-power image processing devices of the future, because a very high density system with an ultra-fine pitch (≤5um) wiring can be fabricated. However, the ultrafine pitch wiring may adversely affect the electrical performance of devices. This paper discusses the signal propagation properties of ultra-fine coplanar interconnects on Si interposers. A design chart of the interconnects, obtained from the viewpoint of maximum line length versus target operating frequency, is presented.

Original language	English
Title of host publication	2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009
Pages	1648-1653
Number of pages	6
DOIs	https://doi.org/10.1109/ECTC.2009.5074236
Publication status	Published - 2009 Oct 12
Event	2009 59th Electronic Components and Technology Conference, ECTC 2009 - San Diego, CA, United States Duration: 2009 May 26 → 2009 May 29

Publication series

Name	Proceedings - Electronic Components and Technology Conference
ISSN (Print)	0569-5503

Conference

Conference	2009 59th Electronic Components and Technology Conference, ECTC 2009
Country	United States
City	San Diego, CA
Period	09/5/26 → 09/5/29

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/ECTC.2009.5074236

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Cite this

Kato, S., Tango, T., Hasegawa, K., Bhandari, R. K., Sakai, A., Segawa, H., Kariya, T., & Sudo, T. (2009). Electrical design and characterization of Si interposer for system-in-package (SiP). In 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009 (pp. 1648-1653). [5074236] (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2009.5074236

Electrical design and characterization of Si interposer for system-in-package (SiP). / Kato, Shinobu; Tango, Tomoyuki; Hasegawa, Kiyohisa; Bhandari, Ramesh K.; Sakai, Atsushi; Segawa, Hiroshi; Kariya, Takashi; Sudo, Toshio.

2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009. 2009. p. 1648-1653 5074236 (Proceedings - Electronic Components and Technology Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kato, S, Tango, T, Hasegawa, K, Bhandari, RK, Sakai, A, Segawa, H, Kariya, T & Sudo, T 2009, Electrical design and characterization of Si interposer for system-in-package (SiP). in 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009., 5074236, Proceedings - Electronic Components and Technology Conference, pp. 1648-1653, 2009 59th Electronic Components and Technology Conference, ECTC 2009, San Diego, CA, United States, 09/5/26. https://doi.org/10.1109/ECTC.2009.5074236

Kato S, Tango T, Hasegawa K, Bhandari RK, Sakai A, Segawa H et al. Electrical design and characterization of Si interposer for system-in-package (SiP). In 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009. 2009. p. 1648-1653. 5074236. (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2009.5074236

Kato, Shinobu ; Tango, Tomoyuki ; Hasegawa, Kiyohisa ; Bhandari, Ramesh K. ; Sakai, Atsushi ; Segawa, Hiroshi ; Kariya, Takashi ; Sudo, Toshio. / Electrical design and characterization of Si interposer for system-in-package (SiP). 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009. 2009. pp. 1648-1653 (Proceedings - Electronic Components and Technology Conference).

@inproceedings{3b44700dfe3f41ff80b6f1d21a58be67,

title = "Electrical design and characterization of Si interposer for system-in-package (SiP)",

abstract = "Si interposer technology has the potential to enable highbandwidth and low-power image processing devices of the future, because a very high density system with an ultra-fine pitch (≤5um) wiring can be fabricated. However, the ultrafine pitch wiring may adversely affect the electrical performance of devices. This paper discusses the signal propagation properties of ultra-fine coplanar interconnects on Si interposers. A design chart of the interconnects, obtained from the viewpoint of maximum line length versus target operating frequency, is presented.",

author = "Shinobu Kato and Tomoyuki Tango and Kiyohisa Hasegawa and Bhandari, {Ramesh K.} and Atsushi Sakai and Hiroshi Segawa and Takashi Kariya and Toshio Sudo",

year = "2009",

month = oct,

day = "12",

doi = "10.1109/ECTC.2009.5074236",

language = "English",

isbn = "9781424444762",

series = "Proceedings - Electronic Components and Technology Conference",

pages = "1648--1653",

booktitle = "2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009",

note = "2009 59th Electronic Components and Technology Conference, ECTC 2009 ; Conference date: 26-05-2009 Through 29-05-2009",

}

TY - GEN

T1 - Electrical design and characterization of Si interposer for system-in-package (SiP)

AU - Kato, Shinobu

AU - Tango, Tomoyuki

AU - Hasegawa, Kiyohisa

AU - Bhandari, Ramesh K.

AU - Sakai, Atsushi

AU - Segawa, Hiroshi

AU - Kariya, Takashi

AU - Sudo, Toshio

PY - 2009/10/12

Y1 - 2009/10/12

N2 - Si interposer technology has the potential to enable highbandwidth and low-power image processing devices of the future, because a very high density system with an ultra-fine pitch (≤5um) wiring can be fabricated. However, the ultrafine pitch wiring may adversely affect the electrical performance of devices. This paper discusses the signal propagation properties of ultra-fine coplanar interconnects on Si interposers. A design chart of the interconnects, obtained from the viewpoint of maximum line length versus target operating frequency, is presented.

AB - Si interposer technology has the potential to enable highbandwidth and low-power image processing devices of the future, because a very high density system with an ultra-fine pitch (≤5um) wiring can be fabricated. However, the ultrafine pitch wiring may adversely affect the electrical performance of devices. This paper discusses the signal propagation properties of ultra-fine coplanar interconnects on Si interposers. A design chart of the interconnects, obtained from the viewpoint of maximum line length versus target operating frequency, is presented.

UR - http://www.scopus.com/inward/record.url?scp=70349666679&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70349666679&partnerID=8YFLogxK

U2 - 10.1109/ECTC.2009.5074236

DO - 10.1109/ECTC.2009.5074236

M3 - Conference contribution

AN - SCOPUS:70349666679

SN - 9781424444762

T3 - Proceedings - Electronic Components and Technology Conference

SP - 1648

EP - 1653

BT - 2009 Proceedings 59th Electronic Components and Technology Conference, ECTC 2009

T2 - 2009 59th Electronic Components and Technology Conference, ECTC 2009

Y2 - 26 May 2009 through 29 May 2009

ER -