EMI reduction by chip-package-board co-design

Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Ryota Kobayashi, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Electromagnetic radiation is always headachy issue in developing various electronic systems. Because electro-magnetic radiation and interference (EMI) is very sensitive to signal routing and physical layout of power distribution network (PDN) in package and board as well as chip design. Therefore, chip-package co-design is becoming important by taking into account the total PDN impedance seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in serious EMI troubles. In this paper, three test chips were designed with different on-chip PDN properties. These three chips were intended to have typical characteristics; oscillatory region and damped condition. Then, the effects of the total PDN impedance on EMI have been studied. In particular, anti-resonance peak was properly suppressed by establishing critical damping condition in chip-package-board co-design. EMI has been proved to be dramatically reduced by proper combination of on-chip capacitance, on-chip resistance and package inductance.

Original languageEnglish
Title of host publicationIEEE International Symposium on Electromagnetic Compatibility
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages946-951
Number of pages6
ISBN (Print)9781479932252
DOIs
Publication statusPublished - 2014 Oct 20
Event2014 International Symposium on Electromagnetic Compatibility, EMC Europe 2014 - Gothenburg
Duration: 2014 Sep 12014 Sep 4

Other

Other2014 International Symposium on Electromagnetic Compatibility, EMC Europe 2014
CityGothenburg
Period14/9/114/9/4

Fingerprint

electromagnetic interference
Signal interference
Electric power distribution
Electromagnetic waves
electromagnetic radiation
chips
Inductance
Capacitance
Damping
impedance
inductance
power supplies
layouts
damping
capacitance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Kiyoshige, S., Ichimura, W., Terasaki, M., Kobayashi, R., & Sudo, T. (2014). EMI reduction by chip-package-board co-design. In IEEE International Symposium on Electromagnetic Compatibility (pp. 946-951). [6931039] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EMCEurope.2014.6931039

EMI reduction by chip-package-board co-design. / Kiyoshige, Sho; Ichimura, Wataru; Terasaki, Masahiro; Kobayashi, Ryota; Sudo, Toshio.

IEEE International Symposium on Electromagnetic Compatibility. Institute of Electrical and Electronics Engineers Inc., 2014. p. 946-951 6931039.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kiyoshige, S, Ichimura, W, Terasaki, M, Kobayashi, R & Sudo, T 2014, EMI reduction by chip-package-board co-design. in IEEE International Symposium on Electromagnetic Compatibility., 6931039, Institute of Electrical and Electronics Engineers Inc., pp. 946-951, 2014 International Symposium on Electromagnetic Compatibility, EMC Europe 2014, Gothenburg, 14/9/1. https://doi.org/10.1109/EMCEurope.2014.6931039
Kiyoshige S, Ichimura W, Terasaki M, Kobayashi R, Sudo T. EMI reduction by chip-package-board co-design. In IEEE International Symposium on Electromagnetic Compatibility. Institute of Electrical and Electronics Engineers Inc. 2014. p. 946-951. 6931039 https://doi.org/10.1109/EMCEurope.2014.6931039
Kiyoshige, Sho ; Ichimura, Wataru ; Terasaki, Masahiro ; Kobayashi, Ryota ; Sudo, Toshio. / EMI reduction by chip-package-board co-design. IEEE International Symposium on Electromagnetic Compatibility. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 946-951
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