Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.

Original languageEnglish
Title of host publicationProceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages91-98
Number of pages8
ISBN (Electronic)9781538674031
DOIs
Publication statusPublished - 2018 Nov 15
Event7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018 - Hakodate, Japan
Duration: 2018 Aug 282018 Aug 31

Other

Other7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
CountryJapan
CityHakodate
Period18/8/2818/8/31

Fingerprint

Flip flop circuits
Sequential circuits
Energy dissipation
Durability
Image processing

Keywords

  • dynamically reconfigurable processor
  • MTJ
  • non-volatile flip-flop
  • power gating
  • process variation
  • thermal fluctuation
  • write energy

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

Cite this

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., ... Yagami, K. (2018). Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. In Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018 (pp. 91-98). [8537701] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NVMSA.2018.00023

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. / Usami, Kimiyoshi; Akaike, Junya; Akiba, Sosuke; Kudo, Masaru; Amano, Hideharu; Ikezoe, Takeharu; Hiraga, Keizo; Shuto, Yusuke; Yagami, Kojiro.

Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 91-98 8537701.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Akaike, J, Akiba, S, Kudo, M, Amano, H, Ikezoe, T, Hiraga, K, Shuto, Y & Yagami, K 2018, Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. in Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018., 8537701, Institute of Electrical and Electronics Engineers Inc., pp. 91-98, 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018, Hakodate, Japan, 18/8/28. https://doi.org/10.1109/NVMSA.2018.00023
Usami K, Akaike J, Akiba S, Kudo M, Amano H, Ikezoe T et al. Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. In Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 91-98. 8537701 https://doi.org/10.1109/NVMSA.2018.00023
Usami, Kimiyoshi ; Akaike, Junya ; Akiba, Sosuke ; Kudo, Masaru ; Amano, Hideharu ; Ikezoe, Takeharu ; Hiraga, Keizo ; Shuto, Yusuke ; Yagami, Kojiro. / Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 91-98
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