Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures

Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Shohei Kawaguchi, Masaomi Sato, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Because CMOS LSIs operate at higher clock frequencies in recent years, conventional methods for obeying EMC regulations are not sufficient only at package level and board level. So chip level counter-measure is even more important to reduce EMI as an excitation source of noise. In this paper, power supply noise was evaluated by fabricating two circuit blocks in a test chip. One was with on-chip capacitance consisted of intentional MOS (metal-oxide semiconductor) capacitors and MIM (metal-insulator-metal) capacitors, and the other was without any intentional capacitors. Reduction effect of power supply noise and the impedance of PDN (power distribution network) at each circuit block were evaluated based on chip-package-board co-design. It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region.

Original languageEnglish
Title of host publicationEMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits
PublisherIEEE Computer Society
Pages142-146
Number of pages5
ISBN (Print)9781479923151
DOIs
Publication statusPublished - 2013 Jan 1
Event9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013 - Nara, Japan
Duration: 2013 Dec 152013 Dec 18

Publication series

NameEMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits

Conference

Conference9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013
CountryJapan
CityNara
Period13/12/1513/12/18

Keywords

  • PDN impedance
  • measurement
  • on-chip capacitance
  • power supply noise

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Fujita, H., Takatani, H., Tanaka, Y., Kawaguchi, S., Sato, M., & Sudo, T. (2013). Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures. In EMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (pp. 142-146). [6735189] (EMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits). IEEE Computer Society. https://doi.org/10.1109/EMCCompo.2013.6735189