Evaluation of power supply noise reduction by implementing on-chip capacitance

Hideyuki Fujii, Yoshinori Kobayashi, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

On-chip decoupling capacitor works to reduce on-chip power supply fluctuation by localizing switching current inside chip. This results in the reduction of electromagnetic interference (EMI) by preventing switching current with high frequency components flowing out from the chip. In this paper, a test chip with on-chip decoupling capacitance and noise generating circuits has been reported using CMOS 0.18 m process. Shoot-through current generator was designed to excite impulse type noise generation. Effects of on-chip capacitance on noise reduction ware evaluated by measuring the test chip as well as by using power supply noise analysis tool. Power supply noise reduction has been quantitatively evaluated by both experiment and analysis.

Original languageEnglish
Title of host publicationProceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011
Pages219-223
Number of pages5
Publication statusPublished - 2011
Event8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011 - Dubrovnik
Duration: 2011 Nov 62011 Nov 9

Other

Other8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011
CityDubrovnik
Period11/11/611/11/9

Fingerprint

Noise abatement
Acoustic noise
Capacitance
Signal interference
Capacitors
Networks (circuits)
Experiments

Keywords

  • CMOS test chips
  • on-chip capacitance
  • power supply noise
  • shoot-through current generator

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Fujii, H., Kobayashi, Y., & Sudo, T. (2011). Evaluation of power supply noise reduction by implementing on-chip capacitance. In Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011 (pp. 219-223). [6130067]

Evaluation of power supply noise reduction by implementing on-chip capacitance. / Fujii, Hideyuki; Kobayashi, Yoshinori; Sudo, Toshio.

Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011. 2011. p. 219-223 6130067.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujii, H, Kobayashi, Y & Sudo, T 2011, Evaluation of power supply noise reduction by implementing on-chip capacitance. in Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011., 6130067, pp. 219-223, 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011, Dubrovnik, 11/11/6.
Fujii H, Kobayashi Y, Sudo T. Evaluation of power supply noise reduction by implementing on-chip capacitance. In Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011. 2011. p. 219-223. 6130067
Fujii, Hideyuki ; Kobayashi, Yoshinori ; Sudo, Toshio. / Evaluation of power supply noise reduction by implementing on-chip capacitance. Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011. 2011. pp. 219-223
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