Power distribution network (PDN) of LSI has become one of important design parameters to reduce simultaneous switching noise for core circuits as well as I/O circuits. Power distribution network of LSI generally consists of meshed power and ground conductors and on-chip decoupling capacitors. For mobile communication and automotive applications, switching current of high-performance CMOS LSIs must be controlled to be low as possible in order to suppress associated electromagnetic interference (EMI). Therefore, on-chip decoupling capacitors must be properly arranged on a chip to optimize the amount of capacitor and to minimize the occupied area by on-chip capacitor. In this paper, a CMOS test chip has been developed which has several test element groups (TEGs) inside. MOS capacitor cells were distributed in each TEG in a different density. Then, an evaluation board was designed to measure the power supply switching current for the each TEG. Furthermore, the power supply switching current was simulated by using a commercial available EDA tool. Reduction level of the switching current was measured and simulated as a function of the value of on-chip decoupling capacitor. Based on both experimental and simulation results, it has been probed that proper density of decoupling capacitor on a chip has been well estimated.