Fast road lane detection by parallel image processor and monocular camera

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Automatic road lane detection is one of the significant problem in Intelligent Transport Systems (ITS). Many studies have been conducted for this interesting problem by using on-vehicle cameras. However, those methods still needs a dozens of milliseconds for image processing. To develop the quick control of the vehicle following lanes, further computational time reduction is expected. Furthermore, regarding the applications, compact hardware is also expected for implementation. Thus, we study on computational time reduction of the road lane detection by using a small-type parallel image processor. Here, computational time is reduced by developing a lane detection algorithm regarding the parallel processing concept of that hardware. According to the experiments, we could limit average computational time for 20 milliseconds with a good lane detection performance.

Original languageEnglish
Title of host publicationWMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings
PublisherInternational Institute of Informatics and Systemics, IIIS
Pages188-191
Number of pages4
Volume2
ISBN (Print)9781941763254
Publication statusPublished - 2015
Externally publishedYes
Event19th World Multi-Conference on Systemics, Cybernetics and Informatics, WMSCI 2015 - Orlando, United States
Duration: 2015 Jul 122015 Jul 15

Other

Other19th World Multi-Conference on Systemics, Cybernetics and Informatics, WMSCI 2015
CountryUnited States
CityOrlando
Period15/7/1215/7/15

Fingerprint

Cameras
Hardware
Image processing
Processing
Experiments

Keywords

  • Image processing
  • Monocular camera
  • Parallel processing
  • Road lane detection

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Premachandra, C. (2015). Fast road lane detection by parallel image processor and monocular camera. In WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings (Vol. 2, pp. 188-191). International Institute of Informatics and Systemics, IIIS.

Fast road lane detection by parallel image processor and monocular camera. / Premachandra, Chinthaka.

WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings. Vol. 2 International Institute of Informatics and Systemics, IIIS, 2015. p. 188-191.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Premachandra, C 2015, Fast road lane detection by parallel image processor and monocular camera. in WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings. vol. 2, International Institute of Informatics and Systemics, IIIS, pp. 188-191, 19th World Multi-Conference on Systemics, Cybernetics and Informatics, WMSCI 2015, Orlando, United States, 15/7/12.
Premachandra C. Fast road lane detection by parallel image processor and monocular camera. In WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings. Vol. 2. International Institute of Informatics and Systemics, IIIS. 2015. p. 188-191
Premachandra, Chinthaka. / Fast road lane detection by parallel image processor and monocular camera. WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings. Vol. 2 International Institute of Informatics and Systemics, IIIS, 2015. pp. 188-191
@inproceedings{3c7e82028725445a9d765292062ee18c,
title = "Fast road lane detection by parallel image processor and monocular camera",
abstract = "Automatic road lane detection is one of the significant problem in Intelligent Transport Systems (ITS). Many studies have been conducted for this interesting problem by using on-vehicle cameras. However, those methods still needs a dozens of milliseconds for image processing. To develop the quick control of the vehicle following lanes, further computational time reduction is expected. Furthermore, regarding the applications, compact hardware is also expected for implementation. Thus, we study on computational time reduction of the road lane detection by using a small-type parallel image processor. Here, computational time is reduced by developing a lane detection algorithm regarding the parallel processing concept of that hardware. According to the experiments, we could limit average computational time for 20 milliseconds with a good lane detection performance.",
keywords = "Image processing, Monocular camera, Parallel processing, Road lane detection",
author = "Chinthaka Premachandra",
year = "2015",
language = "English",
isbn = "9781941763254",
volume = "2",
pages = "188--191",
booktitle = "WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings",
publisher = "International Institute of Informatics and Systemics, IIIS",

}

TY - GEN

T1 - Fast road lane detection by parallel image processor and monocular camera

AU - Premachandra, Chinthaka

PY - 2015

Y1 - 2015

N2 - Automatic road lane detection is one of the significant problem in Intelligent Transport Systems (ITS). Many studies have been conducted for this interesting problem by using on-vehicle cameras. However, those methods still needs a dozens of milliseconds for image processing. To develop the quick control of the vehicle following lanes, further computational time reduction is expected. Furthermore, regarding the applications, compact hardware is also expected for implementation. Thus, we study on computational time reduction of the road lane detection by using a small-type parallel image processor. Here, computational time is reduced by developing a lane detection algorithm regarding the parallel processing concept of that hardware. According to the experiments, we could limit average computational time for 20 milliseconds with a good lane detection performance.

AB - Automatic road lane detection is one of the significant problem in Intelligent Transport Systems (ITS). Many studies have been conducted for this interesting problem by using on-vehicle cameras. However, those methods still needs a dozens of milliseconds for image processing. To develop the quick control of the vehicle following lanes, further computational time reduction is expected. Furthermore, regarding the applications, compact hardware is also expected for implementation. Thus, we study on computational time reduction of the road lane detection by using a small-type parallel image processor. Here, computational time is reduced by developing a lane detection algorithm regarding the parallel processing concept of that hardware. According to the experiments, we could limit average computational time for 20 milliseconds with a good lane detection performance.

KW - Image processing

KW - Monocular camera

KW - Parallel processing

KW - Road lane detection

UR - http://www.scopus.com/inward/record.url?scp=84961125513&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84961125513&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84961125513

SN - 9781941763254

VL - 2

SP - 188

EP - 191

BT - WMSCI 2015 - 19th World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings

PB - International Institute of Informatics and Systemics, IIIS

ER -