Abstract
We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same operating frequency, and thus there is noneed to synchronize neighboring routers working at differentfrequencies. The proposed power management policy makes thesupply voltage of each input and output channel low wheneverthe channel is idle. A MVFG-VP router is designed by using a65nm process and evaluated using a full-system CMP simulator. Evaluation results show that the power consumption is reducedby 33.6% while the performance overhead is only 4.4%compared to a conventional router. In addition, the fine-grainpower management approach is compared to a coarse-grainpower management (for a Multi-Vdd Coarse-Grained VariablePipeline router: MVCG-VP router) that simply controls thesupply voltage of a whole router. The results show that finegrainand less energy overhead approach reduces the powerconsumption by 16.6% compared to the coarse-grain approachwith the same application performance.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012 |
| Pages | 59-66 |
| Number of pages | 8 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012 - Aizu-Wakamatsu, Fukushima Duration: 2012 Sep 20 → 2012 Sep 22 |
Other
| Other | 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012 |
|---|---|
| City | Aizu-Wakamatsu, Fukushima |
| Period | 12/9/20 → 12/9/22 |
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Keywords
- Fine-Grained Power Control
- Low Power
- Network-on-chip
- Router
- Variable pipline
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Fine-grained power control using a multi-voltage variable pipeline router. / Nakamura, Takeo; Matsutani, Hiroki; Koibuchi, Michihiro; Usami, Kimiyoshi; Amano, Hideharu.
Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012. 2012. p. 59-66 6354679.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Fine-grained power control using a multi-voltage variable pipeline router
AU - Nakamura, Takeo
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Usami, Kimiyoshi
AU - Amano, Hideharu
PY - 2012
Y1 - 2012
N2 - We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same operating frequency, and thus there is noneed to synchronize neighboring routers working at differentfrequencies. The proposed power management policy makes thesupply voltage of each input and output channel low wheneverthe channel is idle. A MVFG-VP router is designed by using a65nm process and evaluated using a full-system CMP simulator. Evaluation results show that the power consumption is reducedby 33.6% while the performance overhead is only 4.4%compared to a conventional router. In addition, the fine-grainpower management approach is compared to a coarse-grainpower management (for a Multi-Vdd Coarse-Grained VariablePipeline router: MVCG-VP router) that simply controls thesupply voltage of a whole router. The results show that finegrainand less energy overhead approach reduces the powerconsumption by 16.6% compared to the coarse-grain approachwith the same application performance.
AB - We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same operating frequency, and thus there is noneed to synchronize neighboring routers working at differentfrequencies. The proposed power management policy makes thesupply voltage of each input and output channel low wheneverthe channel is idle. A MVFG-VP router is designed by using a65nm process and evaluated using a full-system CMP simulator. Evaluation results show that the power consumption is reducedby 33.6% while the performance overhead is only 4.4%compared to a conventional router. In addition, the fine-grainpower management approach is compared to a coarse-grainpower management (for a Multi-Vdd Coarse-Grained VariablePipeline router: MVCG-VP router) that simply controls thesupply voltage of a whole router. The results show that finegrainand less energy overhead approach reduces the powerconsumption by 16.6% compared to the coarse-grain approachwith the same application performance.
KW - Fine-Grained Power Control
KW - Low Power
KW - Network-on-chip
KW - Router
KW - Variable pipline
UR - http://www.scopus.com/inward/record.url?scp=84872567302&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84872567302&partnerID=8YFLogxK
U2 - 10.1109/MCSoC.2012.38
DO - 10.1109/MCSoC.2012.38
M3 - Conference contribution
SP - 59
EP - 66
BT - Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012
ER -