Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki

Research output: Contribution to journalArticle

Abstract

Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called "Innovative Power Control for Ultra Low-Power and High-Performance System LSIs", supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.

Original languageEnglish
Pages (from-to)404-412
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE96-C
Issue number4
DOIs
Publication statusPublished - 2013 Apr

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Keywords

  • Compiler
  • Fine grained power-gating
  • Low-power circuit techniques
  • System hierarchy cooperation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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