GaAs buffering circuit ISI for ultra-fast data processing systems

Tadashi Maeda, Y. Miyatake, Y. Tomonoh, S. Asai, M. Ishikawa, K. Nakaizumi, Y. Ohno, N. Ohno, T. Furutsuka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

Original languageEnglish
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
PublisherPubl by IEEE
Pages139-142
Number of pages4
Publication statusPublished - 1988
Externally publishedYes

Fingerprint

LSI circuits
Emitter coupled logic circuits
Refractory metals
Field effect transistors
Metallizing
Energy dissipation
Networks (circuits)
Electric potential
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Maeda, T., Miyatake, Y., Tomonoh, Y., Asai, S., Ishikawa, M., Nakaizumi, K., ... Furutsuka, T. (1988). GaAs buffering circuit ISI for ultra-fast data processing systems. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 139-142). Publ by IEEE.

GaAs buffering circuit ISI for ultra-fast data processing systems. / Maeda, Tadashi; Miyatake, Y.; Tomonoh, Y.; Asai, S.; Ishikawa, M.; Nakaizumi, K.; Ohno, Y.; Ohno, N.; Furutsuka, T.

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, 1988. p. 139-142.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maeda, T, Miyatake, Y, Tomonoh, Y, Asai, S, Ishikawa, M, Nakaizumi, K, Ohno, Y, Ohno, N & Furutsuka, T 1988, GaAs buffering circuit ISI for ultra-fast data processing systems. in Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, pp. 139-142.
Maeda T, Miyatake Y, Tomonoh Y, Asai S, Ishikawa M, Nakaizumi K et al. GaAs buffering circuit ISI for ultra-fast data processing systems. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE. 1988. p. 139-142
Maeda, Tadashi ; Miyatake, Y. ; Tomonoh, Y. ; Asai, S. ; Ishikawa, M. ; Nakaizumi, K. ; Ohno, Y. ; Ohno, N. ; Furutsuka, T. / GaAs buffering circuit ISI for ultra-fast data processing systems. Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, 1988. pp. 139-142
@inproceedings{c4e4487d33644345a8883754d4ab9879,
title = "GaAs buffering circuit ISI for ultra-fast data processing systems",
abstract = "A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.",
author = "Tadashi Maeda and Y. Miyatake and Y. Tomonoh and S. Asai and M. Ishikawa and K. Nakaizumi and Y. Ohno and N. Ohno and T. Furutsuka",
year = "1988",
language = "English",
pages = "139--142",
booktitle = "Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - GaAs buffering circuit ISI for ultra-fast data processing systems

AU - Maeda, Tadashi

AU - Miyatake, Y.

AU - Tomonoh, Y.

AU - Asai, S.

AU - Ishikawa, M.

AU - Nakaizumi, K.

AU - Ohno, Y.

AU - Ohno, N.

AU - Furutsuka, T.

PY - 1988

Y1 - 1988

N2 - A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

AB - A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

UR - http://www.scopus.com/inward/record.url?scp=0024124047&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024124047&partnerID=8YFLogxK

M3 - Conference contribution

SP - 139

EP - 142

BT - Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

PB - Publ by IEEE

ER -