GaAs buffering circuit ISI for ultra-fast data processing systems

T. Maeda; Y. Miyatake; Y. Tomonoh; S. Asai; M. Ishikawa; K. Nakaizumi; Y. Ohno; N. Ohno; T. Furutsuka

GaAs buffering circuit ISI for ultra-fast data processing systems

T. Maeda, Y. Miyatake, Y. Tomonoh, S. Asai, M. Ishikawa, K. Nakaizumi, Y. Ohno, N. Ohno, T. Furutsuka

Research output: Contribution to conference › Paper › peer-review

Abstract

A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

Original language	English
Pages	139-142
Number of pages	4
Publication status	Published - 1988 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@conference{c4e4487d33644345a8883754d4ab9879,

title = "GaAs buffering circuit ISI for ultra-fast data processing systems",

abstract = "A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.",

author = "T. Maeda and Y. Miyatake and Y. Tomonoh and S. Asai and M. Ishikawa and K. Nakaizumi and Y. Ohno and N. Ohno and T. Furutsuka",

year = "1988",

month = dec,

day = "1",

language = "English",

pages = "139--142",

}

TY - CONF

T1 - GaAs buffering circuit ISI for ultra-fast data processing systems

AU - Maeda, T.

AU - Miyatake, Y.

AU - Tomonoh, Y.

AU - Asai, S.

AU - Ishikawa, M.

AU - Nakaizumi, K.

AU - Ohno, Y.

AU - Ohno, N.

AU - Furutsuka, T.

PY - 1988/12/1

Y1 - 1988/12/1

N2 - A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

AB - A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.

UR - http://www.scopus.com/inward/record.url?scp=0024124047&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024124047&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0024124047

SP - 139

EP - 142

ER -

GaAs buffering circuit ISI for ultra-fast data processing systems

Abstract

ASJC Scopus subject areas

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