GaAs high-speed data transfer network for a parallel processing system

Yoshiaki Kitaura, Atushi Kameyama, Toshiyuki Terada, Naotaka Uchitomi, Takeshi Miyagi, Toshio Sudo, Akira Maeda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. In the parallel processing system, a 4-Gb/s data transfer data (32 b × 120 MHz) can be realized by four stacked modules of 48 GaAs BLs.

Original languageEnglish
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages195-198
Number of pages4
Publication statusPublished - 1990 Oct
Event12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC - New Orleans, LA, USA
Duration: 1990 Oct 71990 Oct 10

Other

Other12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC
CityNew Orleans, LA, USA
Period90/10/790/10/10

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kitaura, Y., Kameyama, A., Terada, T., Uchitomi, N., Miyagi, T., Sudo, T., & Maeda, A. (1990). GaAs high-speed data transfer network for a parallel processing system. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 195-198). Piscataway, NJ, United States: Publ by IEEE.