GaAs multichip module for a parallel processing system

Takeshi Miyagi, Kenji Itoh, Susuma Kimijima, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. The total thermal resistance from the chip to the ambient medium was approximately 3°C/W. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by four stacked modules of 48 GaAs BLs.

Original languageEnglish
Title of host publicationProceedings - Electronic Components and Technology Conference
PublisherPubl by IEEE
Pages580-585
Number of pages6
Volume1
Publication statusPublished - 1990
Event1990 Proceedings of the 40th Electronic Components and Technology Conference - Las Vegas, NV, USA
Duration: 1990 May 201990 May 23

Other

Other1990 Proceedings of the 40th Electronic Components and Technology Conference
CityLas Vegas, NV, USA
Period90/5/2090/5/23

Fingerprint

Multichip modules
Data transfer
Parallel processing systems
Data transfer rates
Thin films
Heat pipes
Substrates
Heat resistance
Polyimides
Flow velocity
Resistors
Energy dissipation
Packaging
Multilayers
Cooling
Copper
Air

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Miyagi, T., Itoh, K., Kimijima, S., & Sudo, T. (1990). GaAs multichip module for a parallel processing system. In Proceedings - Electronic Components and Technology Conference (Vol. 1, pp. 580-585). Publ by IEEE.

GaAs multichip module for a parallel processing system. / Miyagi, Takeshi; Itoh, Kenji; Kimijima, Susuma; Sudo, Toshio.

Proceedings - Electronic Components and Technology Conference. Vol. 1 Publ by IEEE, 1990. p. 580-585.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miyagi, T, Itoh, K, Kimijima, S & Sudo, T 1990, GaAs multichip module for a parallel processing system. in Proceedings - Electronic Components and Technology Conference. vol. 1, Publ by IEEE, pp. 580-585, 1990 Proceedings of the 40th Electronic Components and Technology Conference, Las Vegas, NV, USA, 90/5/20.
Miyagi T, Itoh K, Kimijima S, Sudo T. GaAs multichip module for a parallel processing system. In Proceedings - Electronic Components and Technology Conference. Vol. 1. Publ by IEEE. 1990. p. 580-585
Miyagi, Takeshi ; Itoh, Kenji ; Kimijima, Susuma ; Sudo, Toshio. / GaAs multichip module for a parallel processing system. Proceedings - Electronic Components and Technology Conference. Vol. 1 Publ by IEEE, 1990. pp. 580-585
@inproceedings{17bef1d869894b32877e11e755aafeb8,
title = "GaAs multichip module for a parallel processing system",
abstract = "A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. The total thermal resistance from the chip to the ambient medium was approximately 3°C/W. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by four stacked modules of 48 GaAs BLs.",
author = "Takeshi Miyagi and Kenji Itoh and Susuma Kimijima and Toshio Sudo",
year = "1990",
language = "English",
volume = "1",
pages = "580--585",
booktitle = "Proceedings - Electronic Components and Technology Conference",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - GaAs multichip module for a parallel processing system

AU - Miyagi, Takeshi

AU - Itoh, Kenji

AU - Kimijima, Susuma

AU - Sudo, Toshio

PY - 1990

Y1 - 1990

N2 - A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. The total thermal resistance from the chip to the ambient medium was approximately 3°C/W. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by four stacked modules of 48 GaAs BLs.

AB - A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. The total thermal resistance from the chip to the ambient medium was approximately 3°C/W. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by four stacked modules of 48 GaAs BLs.

UR - http://www.scopus.com/inward/record.url?scp=0025544150&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025544150&partnerID=8YFLogxK

M3 - Conference contribution

VL - 1

SP - 580

EP - 585

BT - Proceedings - Electronic Components and Technology Conference

PB - Publ by IEEE

ER -