Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo

Research output: Contribution to journalArticle

10 Citations (Scopus)
Original languageEnglish
Pages (from-to)87-88
Journal16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011
Publication statusPublished - 2011 Jan 26

Cite this

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H., & Kondo, M. (2011). Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating. 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011, 87-88.