Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo

Research output: Contribution to journalArticle

10 Citations (Scopus)
Original languageEnglish
Pages (from-to)87-88
Journal16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011
Publication statusPublished - 2011 Jan 26

Cite this

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., ... Kondo, M. (2011). Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating. 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011, 87-88.

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating. / Zhao, L.; Ikebuchi, D.; Saito, Y.; Kamata, M.; Seki, N.; Kojima, Y.; Amano, H.; Koyama, S.; Hashida, T.; Umahashi, Y.; Masuda, D.; Usami, K.; Kimura, K.; Namiki, M.; Takeda, S.; Nakamura, H.; Kondo, M.

In: 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011, 26.01.2011, p. 87-88.

Research output: Contribution to journalArticle

Zhao, L, Ikebuchi, D, Saito, Y, Kamata, M, Seki, N, Kojima, Y, Amano, H, Koyama, S, Hashida, T, Umahashi, Y, Masuda, D, Usami, K, Kimura, K, Namiki, M, Takeda, S, Nakamura, H & Kondo, M 2011, 'Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating', 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011, pp. 87-88.
Zhao, L. ; Ikebuchi, D. ; Saito, Y. ; Kamata, M. ; Seki, N. ; Kojima, Y. ; Amano, H. ; Koyama, S. ; Hashida, T. ; Umahashi, Y. ; Masuda, D. ; Usami, K. ; Kimura, K. ; Namiki, M. ; Takeda, S. ; Nakamura, H. ; Kondo, M. / Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating. In: 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. 2011 ; pp. 87-88.
@article{e8c0806a15c74b228ea4862c82280282,
title = "Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating",
author = "L. Zhao and D. Ikebuchi and Y. Saito and M. Kamata and N. Seki and Y. Kojima and H. Amano and S. Koyama and T. Hashida and Y. Umahashi and D. Masuda and K. Usami and K. Kimura and M. Namiki and S. Takeda and H. Nakamura and M. Kondo",
year = "2011",
month = "1",
day = "26",
language = "English",
pages = "87--88",
journal = "16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011",

}

TY - JOUR

T1 - Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

AU - Zhao, L.

AU - Ikebuchi, D.

AU - Saito, Y.

AU - Kamata, M.

AU - Seki, N.

AU - Kojima, Y.

AU - Amano, H.

AU - Koyama, S.

AU - Hashida, T.

AU - Umahashi, Y.

AU - Masuda, D.

AU - Usami, K.

AU - Kimura, K.

AU - Namiki, M.

AU - Takeda, S.

AU - Nakamura, H.

AU - Kondo, M.

PY - 2011/1/26

Y1 - 2011/1/26

M3 - Article

SP - 87

EP - 88

JO - 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011

JF - 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011

ER -