Hierarchical symbolic design methodology for large-scale data paths

Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori

Research output: Contribution to journalArticle

Abstract

A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.

Original languageEnglish
Pages (from-to)381-385
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number3
DOIs
Publication statusPublished - 1991 Mar
Externally publishedYes

Fingerprint

Turnaround time
Adders
Microprocessor chips
Masks
Transistors
Compaction
Productivity
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hierarchical symbolic design methodology for large-scale data paths. / Usami, Kimiyoshi; Sugeno, Yukio; Matsumoto, Nobu; Mori, Shojiro.

In: IEEE Journal of Solid-State Circuits, Vol. 26, No. 3, 03.1991, p. 381-385.

Research output: Contribution to journalArticle

Usami, Kimiyoshi ; Sugeno, Yukio ; Matsumoto, Nobu ; Mori, Shojiro. / Hierarchical symbolic design methodology for large-scale data paths. In: IEEE Journal of Solid-State Circuits. 1991 ; Vol. 26, No. 3. pp. 381-385.
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