Hierarchical symbolic design methodology for large-scale datapaths

Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A hierarchical symbolic layout methodology for designing large-scale datapaths is proposed. The methodology constructs a datapath hierarchically by taking note of the bit-slice regular structure. It gives a globally optimized layout with a rapid optimizing loop. This approach has reduced design effort to 1/10 compared with conventional handcraft design (maintaining equivalent layout quality) for a datapath which includes 21K transistors. Macrocells without bit-sliced structure are also considered to be easily embedded into the final datapath layout. Moreover, as a design entry, an LT-diagram entry is allowed for a designer. The diagram is a special logic diagram which includes topological information for gates and wirings. A stick-diagram is automatically synthesized from the LT-diagram and mask layout is generated through compaction.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
Publication statusPublished - 1990
Externally publishedYes
EventProceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA
Duration: 1990 May 131990 May 16

Other

OtherProceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90
CityBoston, MA, USA
Period90/5/1390/5/16

Fingerprint

Electric wiring
Masks
Transistors
Compaction

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Usami, K., Sugeno, Y., Matsumoto, N., & Mori, S. (1990). Hierarchical symbolic design methodology for large-scale datapaths. In Proceedings of the Custom Integrated Circuits Conference Publ by IEEE.

Hierarchical symbolic design methodology for large-scale datapaths. / Usami, Kimiyoshi; Sugeno, Yukio; Matsumoto, Nobu; Mori, Shojiro.

Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, 1990.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Usami, K, Sugeno, Y, Matsumoto, N & Mori, S 1990, Hierarchical symbolic design methodology for large-scale datapaths. in Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90, Boston, MA, USA, 90/5/13.
Usami K, Sugeno Y, Matsumoto N, Mori S. Hierarchical symbolic design methodology for large-scale datapaths. In Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE. 1990
Usami, Kimiyoshi ; Sugeno, Yukio ; Matsumoto, Nobu ; Mori, Shojiro. / Hierarchical symbolic design methodology for large-scale datapaths. Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, 1990.
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