High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications

Yasunori Bito; Yoshiaki Yamakawa; Shinichi Tanaka; Naotaka Iwata

doi:10.1109/LED.2006.879043

High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications

Yasunori Bito, Yoshiaki Yamakawa, Shinichi Tanaka, Naotaka Iwata

Research output: Contribution to journal › Article

1 Citation (Scopus)

Abstract

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p⁺-n junction gate structure for low-voltage-operated mobile applications. The buried p⁺-GaAs gate structure effectively reduced on-resistance (R_on) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p⁺-gate HJFET exhibited a low R_on of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

Original language	English
Pages (from-to)	636-639
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	27
Issue number	8
DOIs	https://doi.org/10.1109/LED.2006.879043
Publication status	Published - 2006 Aug
Externally published	Yes

Fingerprint

Field effect transistors

Threshold voltage

Heterojunctions

Drain current

Voltage measurement

Electric potential

Electric current measurement

Code division multiple access

gallium arsenide

Keywords

Buried gate
Enhancement mode
Heterojunction FET
High efficiency
Low-voltage operation
p-GaAs gate

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Bito, Y., Yamakawa, Y., Tanaka, S., & Iwata, N. (2006). High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications. IEEE Electron Device Letters, 27(8), 636-639. https://doi.org/10.1109/LED.2006.879043

High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications. / Bito, Yasunori; Yamakawa, Yoshiaki; Tanaka, Shinichi; Iwata, Naotaka.

In: IEEE Electron Device Letters, Vol. 27, No. 8, 08.2006, p. 636-639.

Research output: Contribution to journal › Article

Bito, Y, Yamakawa, Y, Tanaka, S & Iwata, N 2006, 'High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications', IEEE Electron Device Letters, vol. 27, no. 8, pp. 636-639. https://doi.org/10.1109/LED.2006.879043

Bito Y, Yamakawa Y, Tanaka S, Iwata N. High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications. IEEE Electron Device Letters. 2006 Aug;27(8):636-639. https://doi.org/10.1109/LED.2006.879043

Bito, Yasunori ; Yamakawa, Yoshiaki ; Tanaka, Shinichi ; Iwata, Naotaka. / High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications. In: IEEE Electron Device Letters. 2006 ; Vol. 27, No. 8. pp. 636-639.

@article{a77e4819730344acbb405ea0db42f773,

title = "High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications",

abstract = "This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9{\%} with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.",

keywords = "Buried gate, Enhancement mode, Heterojunction FET, High efficiency, Low-voltage operation, p-GaAs gate",

author = "Yasunori Bito and Yoshiaki Yamakawa and Shinichi Tanaka and Naotaka Iwata",

year = "2006",

month = "8",

doi = "10.1109/LED.2006.879043",

language = "English",

volume = "27",

pages = "636--639",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications

AU - Bito, Yasunori

AU - Yamakawa, Yoshiaki

AU - Tanaka, Shinichi

AU - Iwata, Naotaka

PY - 2006/8

Y1 - 2006/8

N2 - This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

AB - This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

KW - Buried gate

KW - Enhancement mode

KW - Heterojunction FET

KW - High efficiency

KW - Low-voltage operation

KW - p-GaAs gate

UR - http://www.scopus.com/inward/record.url?scp=33746507397&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33746507397&partnerID=8YFLogxK

U2 - 10.1109/LED.2006.879043

DO - 10.1109/LED.2006.879043

M3 - Article

AN - SCOPUS:33746507397

VL - 27

SP - 636

EP - 639

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 8

ER -

Access to Document

10.1109/LED.2006.879043