High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications

Yasunori Bito; Yoshiaki Yamakawa; Shinichi Tanaka; Naotaka Iwata

doi:10.1109/LED.2006.879043

High-efficiency enhancement-mode power heterojunction FET with Buried p⁺-GaAs gate structure for low-voltage-operated mobile applications

Yasunori Bito, Yoshiaki Yamakawa, Shinichi Tanaka, Naotaka Iwata

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p⁺-n junction gate structure for low-voltage-operated mobile applications. The buried p⁺-GaAs gate structure effectively reduced on-resistance (R_on) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p⁺-gate HJFET exhibited a low R_on of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

Original language	English
Pages (from-to)	636-639
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	27
Issue number	8
DOIs	https://doi.org/10.1109/LED.2006.879043
Publication status	Published - 2006 Aug 1
Externally published	Yes

Keywords

Buried gate
Enhancement mode
Heterojunction FET
High efficiency
Low-voltage operation
p-GaAs gate

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2006.879043

Cite this

@article{a77e4819730344acbb405ea0db42f773,

title = "High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications",

abstract = "This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.",

keywords = "Buried gate, Enhancement mode, Heterojunction FET, High efficiency, Low-voltage operation, p-GaAs gate",

author = "Yasunori Bito and Yoshiaki Yamakawa and Shinichi Tanaka and Naotaka Iwata",

year = "2006",

month = aug,

day = "1",

doi = "10.1109/LED.2006.879043",

language = "English",

volume = "27",

pages = "636--639",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

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TY - JOUR

T1 - High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications

AU - Bito, Yasunori

AU - Yamakawa, Yoshiaki

AU - Tanaka, Shinichi

AU - Iwata, Naotaka

PY - 2006/8/1

Y1 - 2006/8/1

N2 - This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

AB - This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

KW - Buried gate

KW - Enhancement mode

KW - Heterojunction FET

KW - High efficiency

KW - Low-voltage operation

KW - p-GaAs gate

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DO - 10.1109/LED.2006.879043

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

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