High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications

Yasunori Bito, Yoshiaki Yamakawa, Shinichi Tanaka, Naotaka Iwata

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

Original languageEnglish
Pages (from-to)636-639
Number of pages4
JournalIEEE Electron Device Letters
Volume27
Issue number8
DOIs
Publication statusPublished - 2006 Aug
Externally publishedYes

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Keywords

  • Buried gate
  • Enhancement mode
  • Heterojunction FET
  • High efficiency
  • Low-voltage operation
  • p-GaAs gate

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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