This paper presents a high-performance coherent jT/4-shift differential qnantenary phase shift keying (DQPSK) demodulator (large scale integrated circuit) LSIC for the personal communication system in Japan, which is implemented on a 2-V operation 0.8-/im CMOS standard cell. The developed LSIC achieves better bit error rate (BER) and frame error rate (FER) performance and lower power consumption than conventional demodulators by employing new schemes: 1) a reverse-modulation carrier recovery circuit with a -?r/4 phase rotator and a bandwidth-changeable carrier filter; 2) a bit timing recovery circuit using an initial bit timing estimation scheme; and 3) a fully digital orthogonal detector suitable for low power consumption. Performance evaluation confirms that the developed demodulator LSIC reduces the irreducible frame error rate by 40% and achieves an Eb/No improvement of 3 dB at the FER of 10"1 compared with differential detection in the Rayleigh fading typical of personal communication channels.
ASJC Scopus subject areas
- Automotive Engineering
- Aerospace Engineering
- Electrical and Electronic Engineering
- Applied Mathematics