HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME.

Shuji Kubota, K. Ohtani, S. Kato

Research output: Contribution to journal › Article

17 Citations (Scopus)

Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.

Original languageEnglish
Pages (from-to)491-493
Number of pages3
JournalElectronics Letters
Volume22
Issue number9
Publication statusPublished - 1986 Jan 1
Externally publishedYes

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Electric power utilization
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME. / Kubota, Shuji; Ohtani, K.; Kato, S.

In: Electronics Letters, Vol. 22, No. 9, 01.01.1986, p. 491-493.

Research output: Contribution to journal › Article

Kubota, S, Ohtani, K & Kato, S 1986, 'HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME.', Electronics Letters, vol. 22, no. 9, pp. 491-493.
Kubota S, Ohtani K, Kato S. HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME. Electronics Letters. 1986 Jan 1;22(9):491-493.
Kubota, Shuji ; Ohtani, K. ; Kato, S. / HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME. In: Electronics Letters. 1986 ; Vol. 22, No. 9. pp. 491-493.
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