Abstract
A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.
| Original language | English |
|---|---|
| Pages (from-to) | 491-493 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 22 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 1986 Jan 1 |
Keywords
- CMOS LSI
- Codes
- FEC
- Viterbi decoding
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Kubota, S., Ohtani, K., & Kato, S. (1986). High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme. Electronics Letters, 22(9), 491-493. https://doi.org/10.1049/el:19860334