HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME.

Shuji Kubota, K. Ohtani, S. Kato

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.

Original languageEnglish
Pages (from-to)491-493
Number of pages3
JournalElectronics Letters
Volume22
Issue number9
Publication statusPublished - 1986 Jan 1
Externally publishedYes

Fingerprint

Electric power utilization
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME. / Kubota, Shuji; Ohtani, K.; Kato, S.

In: Electronics Letters, Vol. 22, No. 9, 01.01.1986, p. 491-493.

Research output: Contribution to journalArticle

@article{6fb27a21c5fa45938b80e1f433f9cc06,
title = "HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME.",
abstract = "A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.",
author = "Shuji Kubota and K. Ohtani and S. Kato",
year = "1986",
month = "1",
day = "1",
language = "English",
volume = "22",
pages = "491--493",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "9",

}

TY - JOUR

T1 - HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME.

AU - Kubota, Shuji

AU - Ohtani, K.

AU - Kato, S.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.

AB - A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.

UR - http://www.scopus.com/inward/record.url?scp=0022697473&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022697473&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0022697473

VL - 22

SP - 491

EP - 493

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 9

ER -