High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

S. Kubota; K. Ohtani; S. Kato

doi:10.1049/el:19860334

High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

S. Kubota, K. Ohtani, S. Kato

Research output: Contribution to journal › Article › peer-review

17 Citations (Scopus)

Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

Original language	English
Pages (from-to)	491-493
Number of pages	3
Journal	Electronics Letters
Volume	22
Issue number	9
DOIs	https://doi.org/10.1049/el:19860334
Publication status	Published - 1986 Jan 1
Externally published	Yes

Keywords

CMOS LSI
Codes
FEC
Viterbi decoding

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19860334

Cite this

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abstract = "A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.",

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AU - Ohtani, K.

AU - Kato, S.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

AB - A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

KW - CMOS LSI

KW - Codes

KW - FEC

KW - Viterbi decoding

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ER -

High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

Abstract

Keywords

ASJC Scopus subject areas

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