High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

S. Kubota; K. Ohtani; S. Kato

doi:10.1049/el:19860334

High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

S. Kubota, K. Ohtani, S. Kato

Research output: Contribution to journal › Article

17 Citations (Scopus)

Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

Original language	English
Pages (from-to)	491-493
Number of pages	3
Journal	Electronics Letters
Volume	22
Issue number	9
DOIs	https://doi.org/10.1049/el:19860334
Publication status	Published - 1986 Jan 1

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Keywords

CMOS LSI
Codes
FEC
Viterbi decoding

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Kubota, S., Ohtani, K., & Kato, S. (1986). High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme. Electronics Letters, 22(9), 491-493. https://doi.org/10.1049/el:19860334

@article{6fb27a21c5fa45938b80e1f433f9cc06,

title = "High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme",

abstract = "A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.",

keywords = "CMOS LSI, Codes, FEC, Viterbi decoding",

author = "S. Kubota and K. Ohtani and S. Kato",

year = "1986",

month = jan

day = "1",

doi = "10.1049/el:19860334",

language = "English",

volume = "22",

pages = "491--493",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "9",

}

TY - JOUR

T1 - High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

AU - Kubota, S.

AU - Ohtani, K.

AU - Kato, S.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

AB - A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

KW - CMOS LSI

KW - Codes

KW - FEC

KW - Viterbi decoding

UR - http://www.scopus.com/inward/record.url?scp=0022697473&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022697473&partnerID=8YFLogxK

U2 - 10.1049/el:19860334

DO - 10.1049/el:19860334

M3 - Article

AN - SCOPUS:0022697473

VL - 22

SP - 491

EP - 493

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 9

ER -

Access to Document

10.1049/el:19860334