High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

S. Kubota, K. Ohtani, S. Kato

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

Original languageEnglish
Pages (from-to)491-493
Number of pages3
JournalElectronics Letters
Volume22
Issue number9
DOIs
Publication statusPublished - 1986 Jan 1

Keywords

  • CMOS LSI
  • Codes
  • FEC
  • Viterbi decoding

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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